Phase-Change Memory (PCM): Principles & Advances

• Phase-Change Memory (PCM) is a non-volatile memory technology that uses reversible transitions between amorphous and crystalline states via Joule heating for data storage and processing.
• Key methods include detailed electro-thermal modeling, optimized cell architectures, and interface engineering to lower power consumption and boost scalability.
• Emerging trends focus on pulse engineering, coding techniques, and hybrid system integration to improve energy efficiency, endurance, and enable novel in-memory computing platforms.

Phase-Change Memory (PCM) is a non-volatile memory technology in which information is stored by reversibly switching a phase-change material between an amorphous, high-resistance state and a crystalline, low-resistance state through thermally induced phase transitions. In the published literature, PCM is treated simultaneously as a storage-class memory, a candidate for main memory, a platform for multilevel and analog storage, and a substrate for in-memory computing, stateful logic, and cryogenic computation; Ge–Sb–Te alloys, especially Ge$_2$Sb$_2$Te$_5$ (GST) and related compositions, remain the canonical material systems (Burr et al., 2010, Nir-Harwood et al., 27 May 2026).

1. Storage principle and switching physics

PCM stores bits by exploiting the large electrical contrast between amorphous and crystalline phases. In the canonical binary mapping used across the literature, the amorphous phase is the high-resistance RESET state and the crystalline phase is the low-resistance SET state; switching is driven by Joule heating. RESET is obtained by heating above the melting temperature and rapidly quenching, whereas SET is obtained by heating above the crystallization temperature for sufficient time to allow nucleation and growth (Burr et al., 2010, Desai et al., 5 Nov 2025).

A compact electro-thermal description appears repeatedly in PCM work. Fourier heat conduction and volumetric Joule heating are written as

$$\frac{\partial T}{\partial t} = \alpha \nabla^2 T + \frac{Q}{\rho c_p}, \qquad \mathbf{q} = -k \nabla T,$$

with electrical heating power given by $P = I^2 R = V I$ and programming energy by

$E_{\text{prog}} = \int I(t)V(t)\,dt .$

These relations are used to rationalize both device-level switching and array-level operating-current reduction via thermal confinement (Aryana et al., 2020, Neumann et al., 2019, Nir-Harwood et al., 27 May 2026).

A critical enabling mechanism is threshold switching in amorphous material. The 2010 survey reports that threshold switching allows substantial current and efficient Joule heating with applied voltages of order $1\ \mathrm{V}$, and gives the length scaling relation $V_{\text{th}} = E_{\text{th}}L$, with measured $E_{\text{th}}$ spanning $8$–$_2$0 depending on material (Burr et al., 2010). In confined GST cells used for stateful logic, the measured threshold voltage was $_2$1, with threshold switching occurring within $_2$2 during SET (Hoffer et al., 2022).

GST remains the reference material, but the literature includes Ge$_2$3Sb$_2$4Te$_2$5, doped GST, GeTe/Sb$_2$6Te$_2$7 superlattices, TiTe$_2$8-seeded stacks, and electrodeposited GeSbTe. The 2026 review summarizes representative GST parameters for energy estimates as a volumetric heat capacity $_2$9, latent heat of fusion $_5$0, melting temperature $_5$1, and thermal conductivity $_5$2–$_5$3 depending on phase and state (Nir-Harwood et al., 27 May 2026). The same review emphasizes that RESET often has higher instantaneous power, but SET can exceed RESET in total energy because crystallization requires longer pulses (Nir-Harwood et al., 27 May 2026). This directly contradicts the common simplification that RESET necessarily dominates the full programming-energy budget.

2. Cell architectures, confinement strategies, and material integration

PCM device architecture is fundamentally a problem of electro-thermal confinement. The classical survey distinguishes mushroom cells, pore or confined cells, bridge cells, and other contact-minimized or volume-minimized geometries, all designed to reduce RESET current by shrinking the active heated region and controlling heat leakage into electrodes and dielectrics (Burr et al., 2010).

Later work pushed this architectural diversification further. Lateral PCM with graphene ribbon electrodes used atomically sharp graphene “edge” contacts to switch thin GST volumes with threshold voltages as low as $_5$4, programming currents $_5$5 for SET and $_5$6 for RESET, and ON/OFF ratios $_5$7; GST nanoribbon variants often exceeded $_5$8 (Behnam et al., 2015). In mushroom PCM, combining an oxidized TiN filamentary bottom electrode with a monolayer MoS$_5$9 interface reduced RESET current by $$\frac{\partial T}{\partial t} = \alpha \nabla^2 T + \frac{Q}{\rho c_p}, \qquad \mathbf{q} = -k \nabla T,$$0 relative to conventional $$\frac{\partial T}{\partial t} = \alpha \nabla^2 T + \frac{Q}{\rho c_p}, \qquad \mathbf{q} = -k \nabla T,$$1 mushroom cells, while the MoS$$\frac{\partial T}{\partial t} = \alpha \nabla^2 T + \frac{Q}{\rho c_p}, \qquad \mathbf{q} = -k \nabla T,$$2 layer yielded an additional $$\frac{\partial T}{\partial t} = \alpha \nabla^2 T + \frac{Q}{\rho c_p}, \qquad \mathbf{q} = -k \nabla T,$$3 reduction in switching current and peak power (Neumann et al., 2019).

Crossbar-compatible process variants have also been demonstrated. Electrodeposited GeSbTe in microfabricated TiN crossbar arrays achieved a SET/RESET resistance ratio of $$\frac{\partial T}{\partial t} = \alpha \nabla^2 T + \frac{Q}{\rho c_p}, \qquad \mathbf{q} = -k \nabla T,$$4–$$\frac{\partial T}{\partial t} = \alpha \nabla^2 T + \frac{Q}{\rho c_p}, \qquad \mathbf{q} = -k \nabla T,$$5 orders of magnitude with a switching endurance of around $$\frac{\partial T}{\partial t} = \alpha \nabla^2 T + \frac{Q}{\rho c_p}, \qquad \mathbf{q} = -k \nabla T,$$6 cycles, representing the first phase switching of electrodeposited GeSbTe in microfabricated crossbar arrays (Noori et al., 2021). The same work makes clear that this route is promising for scalable, room-temperature, non-line-of-sight deposition, but presently constrained by porosity, carbon incorporation, and cycling-induced segregation (Noori et al., 2021).

Architecture has also diversified beyond conventional memory cells. A six-contact GST device was computationally analyzed as a toggle flip-flop, multiplexer, or demultiplexer by exploiting amorphization-induced isolation and thermal crosstalk-induced recrystallization; interfaced with $$\frac{\partial T}{\partial t} = \alpha \nabla^2 T + \frac{Q}{\rho c_p}, \qquad \mathbf{q} = -k \nabla T,$$7 transistors, it required $$\frac{\partial T}{\partial t} = \alpha \nabla^2 T + \frac{Q}{\rho c_p}, \qquad \mathbf{q} = -k \nabla T,$$8 of the footprint of conventional CMOS alternatives while remaining non-volatile (Khan et al., 2019). Confined GST cells with diameter $$\frac{\partial T}{\partial t} = \alpha \nabla^2 T + \frac{Q}{\rho c_p}, \qquad \mathbf{q} = -k \nabla T,$$9 were used to demonstrate PCM stateful logic gates, including NOR, IMPLY, OR, and NIMP, in single-step operations (Hoffer et al., 2022).

These architectural results collectively suggest that PCM scaling is not reducible to lithographic shrink alone. Contact geometry, electrode composition, interface phase, selector integration, and array parasitics all determine whether a reduction in nominal dimensions translates into lower energy, lower current, or merely higher variability.

3. Energy scaling, pulse engineering, and interface-controlled thermal transport

The modern energy literature identifies two primary levers: minimizing the active phase-change volume and maximizing heat confinement. The 2026 review states that these strategies have already driven PCM to “tens of femtojoules per bit,” while the theoretical adiabatic limit for GST is

$P = I^2 R = V I$0

with practical limits imposed by electrical and thermal parasitics, especially contacts and interfaces (Nir-Harwood et al., 27 May 2026).

Pulse-width engineering is one route to approach that limit. Sub-nanosecond probing of confined via PCM showed that the switching power $P = I^2 R = V I$1 remains essentially unchanged for pulse widths $P = I^2 R = V I$2, so $P = I^2 R = V I$3 decreases linearly as $P = I^2 R = V I$4 is shortened in that regime. The measured thermal time constant was $P = I^2 R = V I$5 in $P = I^2 R = V I$6 diameter devices and $P = I^2 R = V I$7–$P = I^2 R = V I$8 in $P = I^2 R = V I$9–$E_{\text{prog}} = \int I(t)V(t)\,dt .$0 devices. At $E_{\text{prog}} = \int I(t)V(t)\,dt .$1, reset energies reached $E_{\text{prog}} = \int I(t)V(t)\,dt .$2 for a $E_{\text{prog}} = \int I(t)V(t)\,dt .$3 via and $E_{\text{prog}} = \int I(t)V(t)\,dt .$4 for a $E_{\text{prog}} = \int I(t)V(t)\,dt .$5 via, corresponding to energy densities near $E_{\text{prog}} = \int I(t)V(t)\,dt .$6, nearly two orders of magnitude below typical literature values of $E_{\text{prog}} = \int I(t)V(t)\,dt .$7 (Stern et al., 2021).

Interface engineering provides a second, independent axis of improvement. In Ru/W/GST/W/Si stacks characterized by TDTR, the GST–W thermal boundary resistance was strongly phase dependent:

• a-GST/W: $E_{\text{prog}} = \int I(t)V(t)\,dt .$8
• c-GST/W: $E_{\text{prog}} = \int I(t)V(t)\,dt .$9
• h-GST/W: $1\ \mathrm{V}$0

The same study showed that increasing GST–electrode TBR from $1\ \mathrm{V}$1 to $1\ \mathrm{V}$2 reduces $1\ \mathrm{V}$3 by up to $1\ \mathrm{V}$4 in $1\ \mathrm{V}$5 devices and $1\ \mathrm{V}$6 in $1\ \mathrm{V}$7 devices, and can suppress the effective thermal conductivity of a $1\ \mathrm{V}$8 GST layer by $1\ \mathrm{V}$9, from $V_{\text{th}} = E_{\text{th}}L$0 to $V_{\text{th}} = E_{\text{th}}L$1 (Aryana et al., 2020).

The significance of this result is that substantial operating-current reduction can be achieved without introducing separate insulating barriers. Earlier barrier-based approaches did reduce current—C$V_{\text{th}} = E_{\text{th}}L$2 barriers by $V_{\text{th}} = E_{\text{th}}L$3 for SET and single-layer graphene by $V_{\text{th}} = E_{\text{th}}L$4 for RESET—but at costs in electrical resistance, density, or reliability (Aryana et al., 2020). By contrast, GST–W interface phase control and W-thickness reduction tune the TBR directly. The same paper also warns that ultra-thin scaling below $V_{\text{th}} = E_{\text{th}}L$5 can enter a ballistic transport regime in W, increasing leakage and undermining thermal confinement; in a Ru/5 nm W/5 nm GST/5 nm W/Si stack at $V_{\text{th}} = E_{\text{th}}L$6, the measured conductance was $V_{\text{th}} = E_{\text{th}}L$7 versus a diffusive prediction of $V_{\text{th}} = E_{\text{th}}L$8 (Aryana et al., 2020).

Monolayer interfacial barriers are another major line of work. Finite-element modeling of filamentary mushroom PCM with monolayer MoS$V_{\text{th}} = E_{\text{th}}L$9 showed that increasing either electrical contact resistance or TBR alone can yield $E_{\text{th}}$0 improvement in $E_{\text{th}}$1, while increasing both can yield $E_{\text{th}}$2 improvement. In representative $E_{\text{th}}$3, $E_{\text{th}}$4 simulations, programming energy dropped from $E_{\text{th}}$5 in the baseline case to $E_{\text{th}}$6 when both $E_{\text{th}}$7 and TBR were raised (Neumann et al., 2019).

4. Main-memory architectures, coding, and write optimization

At system level, PCM is usually positioned as storage-class memory bridging the latency gap between SSDs ($E_{\text{th}}$8–$E_{\text{th}}$9) and DRAM ($8$0–$8$1) (Song et al., 2020). The principal obstacles are high write latency, high write energy, and operating voltages such as $8$2 and $8$3, which stress peripheral CMOS and aggravate aging mechanisms including TDDB, NBTI, and HCI (Song et al., 2020).

A substantial body of work therefore targets write minimization or write shaping. DATACON exploits the asymmetry between SET-only, RESET-only, and mixed-direction writes by redirecting a logical write to a physical location containing either all-zeros or all-ones content. In the Micron $8$4 PCM model used in the study, overwrite-all-1s writes had $8$5, overwrite-all-0s writes had $8$6, and unknown-content writes had $8$7; the per-bit energies were $8$8 and $8$9, yielding a content threshold near $_2$00 ones (Song et al., 2020). Across SPEC CPU2017, NAS, and ML workloads, DATACON reduced execution time by $_2$01 and access latency by $_2$02 relative to the baseline, while lowering total memory energy by $_2$03 (Song et al., 2020). In the broader system methodology study, DATACON was reported as providing $_2$04 effective access-latency reduction, $_2$05 overall performance improvement, and $_2$06 total memory-system energy reduction versus the best performance-oriented prior technique (Song et al., 2020).

Coding-based approaches attack the same problem from another angle. WIRE assigns codewords to most frequent values so that most writes force at most one-bit flip. In full-system evaluation, WIRE reduced write energy by $_2$07–$_2$08, reduced intra-block write variation by about $_2$09, and improved lifetime by up to $_2$10, at a metadata overhead of $_2$11 bits per $_2$12 block, i.e. $_2$13 (Desai et al., 7 Nov 2025). Thermal constraints can also be expressed directly in coding terms: $_2$14-constrained codes bound the rewrite cost in any $_2$15 consecutive rewrites over any $_2$16 contiguous cells, precisely to limit local heat both in time and space (Qin et al., 2012).

Hybrid and adaptive controllers extend this theme. MNEME uses segmented bitlines and prediction-based placement in a hybrid DRAM–PCM system, placing write-intensive pages preferentially in near DRAM and reducing required operating voltages in near segments; RENEU maps SNN workloads onto PCM-based neuromorphic hardware to balance spike-induced aging, achieving average $_2$17 reduction in circuit aging and $_2$18 lifetime improvement at only $_2$19 performance overhead (Song et al., 2020).

Recent learning-based controllers recast PCM programming as prediction or control. ML-PCM used an MLP multi-output regression model over NVMain data to predict total write energy, total write latency, and endurance per bank with test-set MAPE of $_2$20, $_2$21, and $_2$22, respectively (Desai et al., 5 Nov 2025). SMART-WRITE combined a predictor with PPO-based RL and a temperature-aware voltage model

$_2$23

reporting up to $_2$24 write-energy reduction, up to $_2$25 total-energy reduction, about $_2$26 write-latency improvement, and up to $_2$27 endurance improvement (Desai et al., 5 Nov 2025).

5. Beyond storage: computational memory, logic, cryogenic operation, and optical PCM

PCM has increasingly been used as a computational substrate rather than only as a storage medium. A million-device experimental demonstration used PCM crystallization dynamics to perform temporal correlation detection directly in memory. One million binary stochastic processes were mapped to one million PCM devices; $_2$28 processes formed a correlated group with $_2$29, and the conductance evolution of the assigned devices separated correlated from uncorrelated streams without explicit data movement to a processor (Sebastian et al., 2017).

Digital logic inside PCM has also been demonstrated. A six-contact GST toggle device used amorphization-induced isolation and thermal crosstalk-induced recrystallization to toggle its logic state, functioning as a non-volatile toggle flip-flop with $_2$30 transistors and requiring $_2$31 of the footprint of a conventional CMOS alternative, albeit at roughly $_2$32 versus $_2$33 for CMOS-only designs (Khan et al., 2019). At cell scale, single-step stateful logic gates—NOR, IMPLY, OR, and NIMP—were experimentally demonstrated in confined GST PCM, with $_2$34 and endurance of $_2$35 cycles maintaining a $_2$36 resistance window (Hoffer et al., 2022).

Cryogenic PCM broadens the application space further. Devices characterized from $_2$37 down to $_2$38 retained operable RESET and SET mechanisms, but with qualitatively different transport and noise. The memory window expanded from approximately $_2$39 at $_2$40 to approximately $_2$41 at $_2$42, exceeding a $_2$43 contrast; $_2$44 increased by nearly a factor of two from $_2$45 to $_2$46, but $_2$47 dropped to sub-$_2$48 at $_2$49, and deep-cryogenic matrix–vector multiplication accuracy became comparable to room temperature because drift suppression compensated increased read-noise variability (Lombardo et al., 26 Sep 2025). This suggests PCM is viable for cryogenic in-memory computing relevant to quantum control and deep-space electronics, but only under readout schemes aware of VRH, tunneling, and RDF below $_2$50 (Lombardo et al., 26 Sep 2025).

Optical control defines yet another branch. Optically controlled PCM integrated GST on Si$_2$51N$_2$52 waveguides and used refractive-index contrast, rather than resistance, for multilevel readout. Device prototypes demonstrated $_2$53 stable levels, i.e. up to $_2$54 bits/cell, versus the typical $_2$55 bits/cell in electrically controlled PCM. At architecture level, COSMOS combined OPCM with silicon photonics and an E–O–E control unit, reporting $_2$56 average speedup over EPCM, $_2$57 lower read energy-per-bit, and $_2$58 lower write energy-per-bit (Narayan et al., 2021).

These developments materially weaken the older view that PCM is only a storage-class memory. In current research, PCM is simultaneously a non-volatile analog storage medium, a digital stateful-logic substrate, a cryogenic IMC element, and an optically addressable multilevel device.

6. Reliability, variability, and scaling limits

PCM reliability is dominated by endurance, drift, variability, and interface parasitics. The 2010 survey reported large-array endurance of $_2$59–$_2$60 SET–RESET cycles and single-device endurance up to $_2$61 under favorable conditions, but also identified stuck-RESET and stuck-SET as the dominant failure modes, associated with void formation, delamination, and compositional segregation (Burr et al., 2010). Later system papers more conservatively quote typical endurance of $_2$62–$_2$63 cycles, especially in the context of main-memory wear modeling and write-intensive applications (Desai et al., 5 Nov 2025, Desai et al., 5 Nov 2025). The difference reflects device class, programming regime, and the distinction between favorable single-device conditions and large-system operating assumptions.

Resistance drift remains central, especially for multilevel storage. The 2010 survey gives the standard amorphous-state law

$_2$64

with typical $_2$65–$_2$66 for GST (Burr et al., 2010). Cryogenic characterization refined this picture by separating structural relaxation, partial crystallization, and random drift fluctuations: in fully RESET states the drift exponent was $_2$67, structural-relaxation signatures became indistinct below $_2$68, and stochastic RDF emerged below $_2$69 (Lombardo et al., 26 Sep 2025).

Several recurring misconceptions are corrected by the recent literature. First, simply shrinking the cell does not guarantee lower energy. Below $_2$70 thickness, contact resistance increasingly dominates total resistance, and below $_2$71 GST thickness ballistic heat leakage in adjacent metals can reverse the expected confinement benefit (Nir-Harwood et al., 27 May 2026, Aryana et al., 2020). Second, thermal barriers are not cost-free: added insulators can raise electrical resistance, reduce density, and introduce reliability concerns, which is precisely why interface-phase engineering without extra layers has become important (Aryana et al., 2020). Third, deep-cryogenic operation is not a uniformly beneficial regime: it suppresses monotonic drift and widens dynamic range, but also increases read-noise variability and RDF (Lombardo et al., 26 Sep 2025).

The scaling outlook is therefore asymptotic rather than unbounded. The 2026 review argues that further reductions toward the adiabatic limit require simultaneous optimization of active volume, pulse width, thermal boundary resistance, contact resistivity, selector energy, and interconnect charging energy, because once cell RESET energy approaches tens of femtojoules, array-level interconnect and selector costs become the practical floor (Nir-Harwood et al., 27 May 2026).

Phase-Change Memory therefore occupies a technically distinctive position among non-volatile memories. It is thermally driven rather than filamentary, supports both abrupt binary switching and incremental analog programming, and has evolved from a replacement candidate for NOR or storage-class memory into a broad platform for neuromorphic hardware, logic-in-memory, optical memory, and cryogenic in-memory computing. The most consequential research direction is no longer a single “better cell,” but the co-optimization of material kinetics, interface transport, pulse engineering, array topology, controller policy, and workload mapping (Burr et al., 2010, Nir-Harwood et al., 27 May 2026).