Output-Split C-element (OSC)

• The OSC is a compact CMOS logic primitive with a six-transistor design and cross-coupled PMOS devices enabling simultaneous soft-error protection on inputs and outputs.
• It achieves improved performance by reducing power consumption (40–60% lower) and delay (≈1× inverter delay) compared to standard C-elements while providing post-upset correction.
• The OSC underpins advanced designs like the LOCO latch, delivering enhanced resilience and efficiency in nanometer-scale integrated circuits with single-node upset recovery.

An Output-Split C-element (OSC) is a CMOS logic primitive designed to provide simultaneous protection against soft errors at both its inputs and outputs, as required in resilient storage elements for advanced integrated circuits. It is characterized by a highly compact six-transistor architecture that leverages cross-coupled PMOS transistors for output self-restoration and achieves significant improvements in power, delay, and soft-error tolerance compared to standard C-element implementations. The OSC's dual-output configuration forms the basis of the LOCO latch, a single-node-upset (SNU) self-resilient latch for nanometer-scale CMOS, as detailed by Ma et al. (Ma et al., 22 Dec 2025).

1. Schematic Architecture and Operating Principle

The OSC consists of six transistors organized into pull-up and pull-down stacks, complemented by cross-coupled PMOS devices that serve restoration functionality. The explicit mapping is as follows:

Transistor	Type	Function/Connectivity
M₀, M₁	PMOS	Series pull-up, I₁ and I₂ inputs
M₂, M₃	NMOS	Series pull-down, I₂ and I₁ inputs
M₄, M₅	PMOS	Cross-coupling O₂→O₁, O₁→O₂

Outputs O₁ and O₂ are cross-coupled such that any voltage upset on one can be restored by the other through M₄/M₅. This topology realizes both logical consensus and post-upset correction via local positive feedback.

2. Boolean and State-Machine Description

The OSC implements a stateful logic element whose functional behavior is defined by the following truth table, with I₁, I₂ as binary inputs and O₁, O₂ as dual outputs (Z: high-impedance, previous state retained):

I₁	I₂	(O₁, O₂)
0	0	(1, 1)
1	1	(0, 0)
0	1	(Z, 0)
1	0	(1, Z)

If I₁ = I₂ then $O_1 = O_2 = \neg I_2$. Otherwise, $O_1$ and $O_2$ split roles: one follows its input, the other holds the prior state. This redundancy and output-splitting are central to the OSC's resilience against transient faults.

3. Soft-Error and Upset Protection Mechanism

The OSC's novel contribution lies in its simultaneous input and output filtering:

• For an SNU on I₁ or I₂, at most one output is transiently corrupted; the healthy output restores state via the cross-coupled PMOS after the transient dissipates.
• For an SNU on O₁ or O₂, the companion output instantaneously restores the corrupted node.
• Thus, the OSC does not require ancillary output filters and inherently "heals" SNUs on both sides, differing fundamentally from conventional C-elements that only filter at the input and leave their single output unprotected (Ma et al., 22 Dec 2025).

4. Soft-Error Filtering and Performance Metrics

Two primary analytical models are used:

• Single-Event Transient (SET) Injection:

$$I_{\mathrm{inj}}(t) = \frac{Q_{\mathrm{inj}}}{\tau_1-\tau_2}\left(e^{-t/\tau_1} - e^{-t/\tau_2}\right)$$

Typical time constants are $\tau_1 = 0.1\,\mathrm{ps}$, $\tau_2 = 3\,\mathrm{ps}$.

• Short-Circuit Current (power metric):

$$I_{\mathrm{avg}} = \frac{1}{t_1 - t_0} \int_{t_0}^{t_1}|I_{\mathrm{VDD}}(t)|dt$$

This measures switching-induced power dissipation.

Experimentally, the OSC reduces short-circuit current by 40–60% under switching, attributed to its single-transistor pull network and high-impedance output in disagree cases.

5. Comparison with Conventional C-Element Designs

The OSC exhibits several advantages relative to standard static CMOS C-elements:

Metric	2-Input C-Element	OSC
#Transistors	6P+6N (or 3P+3N+inv)	6 total
Propagation delay	≈2× inverter	≈1× inverter
Short-circuit power	Higher	40–60% lower
SNU resilience	Input only	Inputs and outputs (both)

While a classic C-element only filters SNUs on its inputs, the OSC's cross-coupling allows dual-side protection and self-restoration, eliminating the need for output-stage hardening (Ma et al., 22 Dec 2025).

6. System-Level Impact: LOCO Latch Performance

The OSC forms the core of the LOCO SNU-resilient latch, which is evaluated against alternative hardened latches. Salient normalized results (from the LOCO paper):

Latch	#Trans	Power (µW)	Avg Delay (ps)	PDP ($10^{-18}$ J)	$Q_{\mathrm{crit}}$ (fC)
RFC	0.28	6.80	5.58	1.59	12.12
ISEHL	0.67	11.50	5.54	3.70	20.52
RFEL	0.64	1.90	53.67	34.54	24.69
HIDER	0.35	1.70	24.66	8.57	16.43
LOCO	0.18	6.90	5.24	0.93	9.06

On average, LOCO achieves 19.3% fewer transistors, 63.6% lower power, 74.5% less delay, and 92.3% lower PDP relative to the robust comparators, while maintaining high critical charge for SNU resilience (Ma et al., 22 Dec 2025).

7. Complementary Techniques: Power and Speed Optimization

The integration of OSC in LOCO is complemented by:

• Clock-gating: A CLKB-controlled NMOS transistor (MN6) disables unnecessary toggling during the hold phase, decreasing dynamic power consumption.
• Fast data path: When the clock (CLK) is high, a dedicated transmission gate (TG₀) relays D-to-Q directly, bypassing OSC feedback and minimizing D-to-Q latency.

These techniques align with the OSC's inherent low-power and low-latency characteristics, enabling practical deployment in nanometer-scale, soft error-prone digital systems.

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For further detail, see Ma et al., "LOCO: A Low-Cost SNU-Self-Resilient Latch Using an Output-Split C-Element" (Ma et al., 22 Dec 2025).