3RSeT: Reducing Read Disturbance in STT-MRAM Caches

• The paper introduces the 3RSeT mechanism to selectively filter tag comparisons in STT-MRAM caches, reducing tag bit-read counts by approximately 71.8% and improving MTTF by 3.6×.
• It employs a two-stage comparison using a 4-bit LSB filter to preclude non-matching tags and then performs full MSB comparison, resulting in significant energy savings with negligible area overhead.
• Evaluation via a gem5 cycle-accurate simulator demonstrates that 3RSeT dramatically lowers tag disturbance rates and dynamic energy consumption compared to traditional mitigation strategies.

Spin-Transfer Torque Magnetic RAM (STT-MRAM) has emerged as a leading candidate to replace SRAM in on-chip cache memories due to its lower leakage power, higher density, non-volatility, and inherent resistance to radiation-induced faults. Despite these advantages, STT-MRAM suffers from read disturbance errors—unintentional bit flips during read operations—which are particularly problematic in tag arrays of set-associative caches. The 3RSeT mechanism (Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison) introduces a low-cost architectural method to minimize tag-array read disturbance by disabling the majority of unnecessary tag reads on each access. This approach achieves substantial reductions in bit-read counts, dramatic improvements in Mean Time To Failure (MTTF), and significant energy savings with negligible area overhead (Cheshmikhani et al., 27 Nov 2025).

1. Read Disturbance Errors in STT-MRAM Tag Arrays

Read disturbance in STT-MRAM arises from the fundamental operation of the Magnetic Tunnel Junction (MTJ) device. During a read, current $I_{\text{read}}$ flows through the MTJ, chosen to be less than the write switching threshold $I_{C0}$. However, statistical thermal fluctuations and device-level variability introduce a finite probability that this current induces a spontaneous flip of the free-layer magnetization (a read-disturbance error). The probability of disturbance per read, governed by the Néel–Arrhenius law, is: $$P_{\text{RD}} = 1 - \exp\left(-\frac{t_{\text{read}}}{\tau \exp[\Delta (1 - I_{\text{read}}/I_{C0})]}\right)$$ where $t_{\text{read}}$ is the read-pulse width, $\tau$ is the attempt period (≈1 ns), $\Delta=E_b/(k_B T)$ is the thermal-stability factor, with $E_b$ the MTJ's energy barrier, $k_B$ Boltzmann’s constant, and $T$ absolute temperature.

Tag arrays in $k$-way associative STT-MRAM caches are a point of vulnerability because, for every read or write cache access, all $I_{C0}$0 tag ways are simultaneously read and compared to the access request's tag. This practice leads to frequent, cumulative exposure of tag bits to read disturbance events, with the probability of a cell flip after $I_{C0}$1 reads given by: $I_{C0}$2 Given high read locality and parallel reading of all tag ways, the disturbance risk scales with $I_{C0}$3.

2. Tag-Array Read Access Patterns and Accumulated Disturbance

Standard set-associative cache access requires all $I_{C0}$4 tag ways to be read in parallel for every access (read or write), enabling tag comparison and hit/miss determination. For each cache access, $I_{C0}$5 tag reads are performed, but the data array is only accessed on a hit or following replacement decisions. The total exposure of a tag cell to reads before the next write is $I_{C0}$6, where $I_{C0}$7 is the request stream length and $I_{C0}$8 the average interval between writes to the tag line. This design pattern creates a disproportionate read frequency in the tag array relative to the data array, driving rapid accumulation of read-disturbance risk.

3. 3RSeT Selective Tag Comparison Mechanism

3RSeT introduces a two-stage tag comparison mechanism that capitalizes on partial tag discrimination using low-significance bits (LSBs) to prefilter and disable non-matching tag ways before full tag comparison.

• Stage 1 (LSB Filter): The $I_{C0}$9 least significant bits (LSBs) of all $$P_{\text{RD}} = 1 - \exp\left(-\frac{t_{\text{read}}}{\tau \exp[\Delta (1 - I_{\text{read}}/I_{C0})]}\right)$$0 tag ways are read and compared in parallel against the corresponding LSBs of the access tag. Ways with mismatched LSBs are disabled for this access and excluded from subsequent high-order comparison.
• Stage 2 (MSB Comparison): Only the $$P_{\text{RD}} = 1 - \exp\left(-\frac{t_{\text{read}}}{\tau \exp[\Delta (1 - I_{\text{read}}/I_{C0})]}\right)$$1 most significant bits (MSBs) of surviving tag ways are read and compared.

For 31-bit tags ($$P_{\text{RD}} = 1 - \exp\left(-\frac{t_{\text{read}}}{\tau \exp[\Delta (1 - I_{\text{read}}/I_{C0})]}\right)$$2) and $$P_{\text{RD}} = 1 - \exp\left(-\frac{t_{\text{read}}}{\tau \exp[\Delta (1 - I_{\text{read}}/I_{C0})]}\right)$$3-way set associativity, $$P_{\text{RD}} = 1 - \exp\left(-\frac{t_{\text{read}}}{\tau \exp[\Delta (1 - I_{\text{read}}/I_{C0})]}\right)$$4 is shown to be optimal across all SPEC2006 multi-program workloads, with the LSB filter typically rejecting 93.75% of tag ways. The average number of ways passing the 4-bit LSB filter ($$P_{\text{RD}} = 1 - \exp\left(-\frac{t_{\text{read}}}{\tau \exp[\Delta (1 - I_{\text{read}}/I_{C0})]}\right)$$5) is observed to be $$P_{\text{RD}} = 1 - \exp\left(-\frac{t_{\text{read}}}{\tau \exp[\Delta (1 - I_{\text{read}}/I_{C0})]}\right)$$6 on hits and even fewer on misses.

Hardware Implementation consists of:

1. Index decode and word-line activation for $$P_{\text{RD}} = 1 - \exp\left(-\frac{t_{\text{read}}}{\tau \exp[\Delta (1 - I_{\text{read}}/I_{C0})]}\right)$$7 ways.
2. Selective sense path enabling for LSBs via a dedicated transistor (“Ctrl1”).
3. Parallel 4-bit comparison for each way, setting individual latch signals.
4. Latch output enables (“Ctrl2”) for MSB word lines only for matching ways.
5. In the same cycle, once LSB comparison is resolved, the controller gates LSB paths and activates MSB paths according to latches; full tag comparison is completed on this subset.

This mechanism ensures that, on each access, tag reads are reduced to $$P_{\text{RD}} = 1 - \exp\left(-\frac{t_{\text{read}}}{\tau \exp[\Delta (1 - I_{\text{read}}/I_{C0})]}\right)$$8 (LSBs) plus $$P_{\text{RD}} = 1 - \exp\left(-\frac{t_{\text{read}}}{\tau \exp[\Delta (1 - I_{\text{read}}/I_{C0})]}\right)$$9 (MSBs), substantially less than the conventional $t_{\text{read}}$0 bit-reads per access.

4. Quantitative Impact and Evaluation

Extensive evaluation using a gem5 cycle-accurate full-system simulator (4-wide, OOO, 3 GHz core; private L1 32 KiB, shared L2 1 MiB STT-MRAM, 64 B lines, 31-bit tags, SPEC CPU2006 workloads) demonstrates the following impact:

Metric	Baseline	3RSeT	Percent Change
Tag array bit-reads/access	$t_{\text{read}}$1	$t_{\text{read}}$2	$t_{\text{read}}$3
Tag disturbance rate	1.0×	0.282×	$t_{\text{read}}$4
MTTF	1.0×	3.6×	$t_{\text{read}}$5
Tag array energy	1.0×	0.379×	$t_{\text{read}}$6
Area overhead	—	$t_{\text{read}}$7	—

The proportionality $t_{\text{read}}$8 yields the 3.6× MTTF improvement, as the disturbance probability is reduced to $t_{\text{read}}$9 of baseline. Dynamic energy usage in the tag array is reduced by $\tau$0 based solely on bit-read counts, with total energy (including sense amplifier overhead) reduced by $\tau$1. Hardware additions per way—one 4-bit comparator, one 27-bit comparator, a 4-bit sense amplifier, two NMOS control transistors, one S/R latch, one AND, one inverter—correspond to less than $\tau$2 of the total L2 cache area.

5. Comparison to Prior Mitigation Approaches

Conventional read-disturbance mitigation strategies in STT-MRAM data arrays include ECCs/EED codes (which incur prohibitive energy and area cost in tags), read–restore/flip-back schemes (requiring post-read writebacks, adding large energy and time overhead), and device-level circuit biasing (reducing read current at the expense of sense speed and marginal benefit). None directly address the unique, highly-read nature of the tag array.

Prior tag-energy optimization methods from SRAM cache literature—such as way prediction, halt tags, or partial tags—fail to provide effective mitigation in large L2 caches (due to prediction accuracy loss and need for fully associative storage), and do not reduce tag bit-reads. By exclusively targeting the tag array with selective disabling and without introducing misprediction or performance loss, 3RSeT uniquely achieves both reliability (3.6× MTTF) and energy (62.1% reduction) at sub-0.4% area cost and no impact on CPI.

6. Limitations and Future Work

3RSeT focuses exclusively on tag-array read disturbance; mitigation of data array errors remains the domain of ECC or REAP‐Cache schemes. The $\tau$3 LSB split, optimal for SPEC2006 multi-program workloads, may require retuning for different cache configurations or workload characteristics. A plausible implication is that a dynamic LSB length predictor could further optimize filtering efficiency by adapting $\tau$4 to runtime access locality. Wider physical addresses (e.g., 52–64 bit), resulting in longer tags, may amplify the benefits of LSB-based filtering. The additional combinational logic path introduced by the controller is shown not to impact critical-path delay, as it remains below data-array latency, thus maintaining zero performance cost.