Non-Local Best Effort Routing

• Non-local best effort routing is a class of algorithms that integrate global topological information with local, resource-aware rules to optimize network connectivity.
• In quantum hardware, the HAL framework uses techniques such as community detection and force-directed layouts to efficiently embed qubit graphs into multi-layer grids while adhering to strict hardware constraints.
• For communication networks, these methods balance projected waiting times to prevent congestion, effectively delaying jamming and dynamically distributing load across nodes.

Non-local best effort routing comprises a class of routing algorithms designed to optimize the assignment and traversal of network connections when global resource or topological constraints preclude strictly local, shortest-path solutions. These algorithms operate on both physical hardware placement problems—such as embedding quantum error correcting codes (QECCs) into multi-layer superconducting qubit architectures—and communication network packet delivery, as demonstrated in scale-free and complex network models. Their defining feature is the integration of non-local information at decision points, combined with locally adaptive, resource-aware heuristics to achieve high-quality connectivity or message delivery under practical constraints.

1. Formal Frameworks and Problem Definitions

In quantum hardware layout, non-local best effort routing concerns embedding a connectivity graph $G=(V,E)$, where $V$ are qubits and $E$ are required two-qubit couplers, into a multi-layer 3D grid $\mathcal G = \mathbb Z^2 \times \{0,1,\ldots,L-1\}$ representative of the hardware architecture. Each qubit occupies a unique position on the qubit tier ($z = 0$), and routing tiers ($z > 0$) enable additional connectivity via flip-chip interfaces and TSVs (through-silicon vias). Placement comprises mapping $V$ to grid positions; routing comprises assigning discrete paths $(x_0,y_0,z_0) \to \ldots \to (x_k,y_k,z_k)$ for each edge, subject to constraints: no trace crossings per grid cell/layer (C1), bounded bump transitions per edge ($B_{\max}$; C2), bounded TSV usage ($T_{\max}$; C3), and optional maximum path-length (C4) (Mathews et al., 30 Jul 2025).

In communication networks, the non-local best effort paradigm is exemplified by algorithms that, at each forwarding step, consider not only immediate neighbor states but projected congestion or waiting time along the path to the destination. In Barabási–Albert scale-free (SF) networks, each node $i$ generates packets proportional to its degree ($\lambda k_i$) and forwards up to $1+\beta k_i$ per time step, with routing decisions based on minimizing the sum of expected waiting times over the full shortest path from each neighbor to the destination (0806.1843).

2. Algorithmic Principles and Cost Functions

The hardware-aware layout algorithm HAL implements non-local best effort routing through a combination of placement and routing phases. Placement extracts a planar subgraph $G_0$ by community detection and planarity tests (Hopcroft–Tarjan), maximizing local connectivity. Nodes are embedded using force-directed spring layouts (Kamada–Kawai), then rasterized to the integer grid with conflict resolution and compaction. Routing proceeds by packing as many couplers as feasible on the qubit tier, using straight-line attempts, bump transitions, and, upon blockage, escalating traces to higher routing tiers via TSVs. Routing in each tier employs straight-line and A* search heuristics, subject to bump and TSV budgets. All steps operate via graph-and-grid heuristics, with no global solver; tier escalation is strictly limited to necessity, optimizing coupler path lengths and hardware resource use (Mathews et al., 30 Jul 2025).

Objective functions in HAL comprise four metrics: number of tiers used ($q_1$), average edge length ($q_2$), maximal average bump bonds per edge per layer ($q_3$), and average TSVs per edge in $z \ge 1$ layers ($q_4$). Each metric is rescaled between baseline (surface code hardware) and optimistic targets, then the aggregate cost $C_{\rm hw}$ is computed as a weighted sum: $$C_{\rm hw} = 1 + \frac{\sum_{i=1}^4 w_i c_i}{\sum_{i=1}^4 w_i}$$ where $w_i$ are weights (uniform by default), $c_i$ is the normalized metric, and $C_{\rm hw}=1$ signifies a single-tier, nearest-neighbor layout (Mathews et al., 30 Jul 2025).

In network communication, the key decision metric is the projected waiting time: $$W_{i\to d}(\ell) = \sum_{s \in SP(\ell \to d)} \frac{n_s}{1+\beta k_s}$$ where $n_s$ is the instantaneous queue length at node $s$, $k_s$ its degree, $\beta$ the forwarding enhancement, and $SP(\ell \to d)$ the deterministic shortest path from neighbor $\ell$ to destination $d$. Each packet is forwarded to the neighbor $\ell^*$ minimizing this sum, thereby balancing load while avoiding congested hubs (0806.1843).

3. Heuristics, Subroutines, and Implementation Details

HAL’s workflow separates placement from routing. In placement, the Louvain algorithm clusters vertices; edges are sorted by community and Euclidean length; feasible edges populate $E_0$ by incremental planarity testing, non-planar edges are deferred to routing on higher tiers. The force-directed layout minimizes $\sum_{u<v}(d_E(p_u,p_v)-d_G(u,v))^2$, ensuring geometric proximity reflects the code graph. Rasterization and compaction adapt the layout to the hardware grid.

Routing consists of sequential edge attempts per tier. Straight-line routing is attempted first; blocked paths may invoke bump transitions (flip-chip side changes). Unroutable or over-budget edges are escalated via TSVs. Within each tier, edges are processed by ascending straight-line length; A* search is used for complex paths, exploring cardinal, diagonal, and vertical bump moves, pruning over-budget or conflicting trace candidates. Each step enforces local constraints, and if routing fails at maximum allowed tier, the edge remains unrouted (Mathews et al., 30 Jul 2025).

In packet delivery networks, each node forwards packets by evaluating projected waiting times for all neighbors; ties are broken uniformly at random. Mean-field analysis tracks queue dynamics as functions of node degree and global generation/forwarding rates. Storing shortest-path tables for all node pairs requires $O(N^2)$ space; in practice, routing scales linearly in $N$ for sparse networks, with per-hop calculations $O(\langle k \rangle \cdot D)$ (0806.1843).

4. Hardware and Network Constraints

In HAL, strict hardware constraints are enforced per edge and per layer: grid cell occupancy prohibits trace crossings (C1), bump and TSV budgets are never exceeded per edge (C2–C3), and coupler lengths may be bounded (C4). Flip-chip crosstalk is managed by allowing crossings on opposite sides but bump transitions are counted as costs. When routing demands exceed current tier budgets, TSVs convey traces to higher tiers, escalating only as needed (Mathews et al., 30 Jul 2025).

In complex network routing, the primary constraints are node degree-dependent packet generation and service capacity ($\lambda k_i$ and $1+\beta k_i$). Jamming arises when hub nodes saturate their queues; non-local best effort routing delays jamming and maintains network throughput by shifting load to underutilized paths, avoiding shortest-path-overload phenomena (0806.1843).

5. Performance Metrics and Empirical Findings

HAL achieves hardware-efficient layouts for arbitrary QECC families. Empirical runtime scaling is $O(E)$ for structured codes (e.g., bivariate bicycle) and up to $O(E^3)$ for general random connectivity, with large codes ($\llbracket 416,18,26\rrbracket$, 15,225 edges) solvable in $\approx 2$ hours on a single CPU. In three code comparisons, bivariate bicycle ($\llbracket 144,12,12\rrbracket$) and radial ($\llbracket 126,8,14\rrbracket$) require 5 tiers, with average edge lengths $11.08$ and $13.19$, bumps $5.06$ and $5.30$, TSVs $3.27$ and $3.16$; open-boundary tile code ($\llbracket 188,8,9\rrbracket$) needs only 3 tiers, with edge length $2.98$, bumps $2.89$, TSVs $2.17$, and markedly lower hardware cost ($C_{\rm hw} = 1.54$). Large-scale studies plot $C_{\rm hw}$ against logical efficiency $\eta_L=k d^2/n$, confirming a trade-off: codes with higher logical efficiency typically demand greater hardware resources. Low-weight radial codes achieve competitive efficiency with minimal hardware overhead (Mathews et al., 30 Jul 2025).

In communication networks, non-local best effort routing yields lower critical delivery capacity $\beta_c(\lambda)$ compared to shortest-path or localized waiting-time schemes. For BA networks ($N=1000$, $m=3$, $\langle k \rangle=6$), the method delays jamming transition, maintains free flow (mean queue length $n_k \propto k$), and distributes workloads according to node capabilities. Mean delivery time and queue order parameters saturate in free-flow regime and grow linearly in jamming (0806.1843).

6. Conceptual Significance and Generalizations

Non-local best effort routing synthesizes topological optimization (shortest paths, minimization of coupler lengths) with dynamic constraint adaptation (congestion, hardware tier escalation, queue management). By evaluating projected cost over entire paths or escalating connectivity only as necessary, such schemes retain much computational efficiency while accommodating resource limitations inherent in physical and communication networks. In quantum hardware contexts, these algorithms enable the feasibility assessment and optimization of non-local QECCs, facilitating larger qubit arrays and lower code overheads. In complex networks, they realize high-throughput, congestion-averse delivery without global coordination, self-organizing load distribution according to node capability.

This suggests that non-local best effort routing constitutes a general strategy for managing complex connectivity and delivery tasks in resource-constrained, adaptive systems, with empirical and theoretical advantages confirmed across physical and abstract network domains (Mathews et al., 30 Jul 2025, 0806.1843).

7. Comparative Analysis

A tabular summary of HAL performance for selected QECCs:

Code Type (parameters)	Tiers Used	Av. Edge Length	Av. Bumps	Av. TSVs	Hardware Cost $C_{\rm hw}$
Bivariate bicycle ($\llbracket 144,12,12\rrbracket$)	5	11.08	5.06	3.27	2.12
Radial ($\llbracket 126,8,14\rrbracket$)	5	13.19	5.30	3.16	2.18
Tile ($\llbracket 188,8,9\rrbracket$)	3	2.98	2.89	2.17	1.54

Such data highlight the quantitative impact of code structure (planarity, boundary conditions) on routing resource requirements. A plausible implication is the strategic selection or design of codes with favorable routing overhead, given hardware constraints (Mathews et al., 30 Jul 2025).