NeuronML Silicon Neuron Algorithm

• NeuronML Algorithm is a neuromorphic design that uses current-mode circuits and time-scale separation to emulate biologically robust spiking and bursting behaviors.
• It employs modular Differential-Pair Integrators and current-mode sigmoid blocks to achieve adaptive neuromodulation across fast, slow, and ultraslow dynamics.
• Experimental results validate energy efficiency, stable bifurcations, and resilience to temperature and fabrication variations in CMOS implementations.

Current-mode neuromodulable silicon neurons are analog and mixed-signal electronic circuits specifically engineered to emulate the neuromodulatory adaptability and robustness of biological neurons using current-mode signaling and time-scale separated feedback loops. These devices leverage minimal, modular architectures—primarily constructed from Differential-Pair Integrators (DPIs) and current-mode sigmoid comparator blocks—to realize excitability, tonic spiking, and burst-firing patterns in CMOS and bipolar silicon technologies. Their operation, tuning, and design principles adhere closely to singularity theory and bifurcation frameworks derived from high-dimensional conductance-based models, ensuring both robust neuromodulation and resilience to variations in input current, temperature, and fabrication process.

1. Circuit Architecture and Building Blocks

Current-mode neuromodulable silicon neurons, as presented in "A Neuromodulable Current-Mode Silicon Neuron for Robust and Adaptive Neuromorphic Systems" (Mendolia et al., 30 Nov 2025), consist of three primary subcircuits, each implemented as a Differential-Pair Integrator (DPI) responsible for fast, slow, and ultraslow integration. Two additional current-mode sigmoidal (comparator-gain) blocks introduce positive feedback and inactivation. The neuron operates entirely in the current domain, mapping analog membrane potential physics onto circuit currents.

Key elements include:

• Fast DPI Integrator: Implements rapid membrane current integration ($I_f$), analogous to action potential initiation.
• Slow and Ultraslow DPI Integrators: Generate slower adaptation ($I_s$) and even slower accommodation ($I_u$) currents, regulating repolarization and spike-frequency adaptation.
• Current-mode Sigmoid Blocks: Inject regenerative positive feedback in fast ($\mathcal S_f$) and slow ($\mathcal S_s$) paths, with dynamic gain modulation via inactivation.
• Inactivation Mechanisms: Subtract slow and ultraslow currents from the respective comparator gain bias, achieving context-dependent regulation of neuron excitability and burst termination.

Implementations in standard 180 nm CMOS processes yield core neuron areas of approximately $3800\,\mu\text{m}^2$ with a rest power consumption near $3\,\text{nW}$, and instantaneous spiking power around $10\,\text{nW}$.

2. Mathematical Models and Dynamical Framework

The circuit dynamics are governed by three coupled differential equations with explicit time-scale separation: $$\begin{aligned} \tau_f \frac{dI_f}{dt} &= -I_f + G_f[\mathcal S_f(I_f;I_{G_f}) + \mathcal S_s(I_s;I_{G_s}) - I_s - I_u + I_{app}], \ \tau_s \frac{dI_s}{dt} &= -I_s + G_s I_f, \ \tau_u \frac{dI_u}{dt} &= -I_u + G_u I_f. \end{aligned}$$ where $I_f$ is the fast (membrane-like) current, $I_s$ and $I_u$ are the slow and ultraslow adaptation currents, and $I_{app}$ is the applied input current. The sigmoidal feedback functions $\mathcal S_f$ and $\mathcal S_s$ are realized as current-mode comparators with dynamically inactivated biases.

Neuromodulation is effected by biasing the slow positive feedback gain ($I_{G_s,0}$); increased $I_{G_s,0}$ smooths the transition from tonic spiking to bursting states. Inactivation dynamically modifies the gain parameters: $I_{G_f} = I_{G_f,0} - I_s$ and $I_{G_s} = I_{G_s,0} - I_u$, allowing for real-time context-dependent adaptation.

3. Principles of Neuromodulation and Time-Scale Separation

Physiological neuromodulation is emulated by tuning current-source bias voltages associated with slow ($I_{G_s}$) and ultraslow ($I_{G_u}$) feedback loops. This direct control of feedback gain reshapes static current–output (I–I) curves, which define the excitability and firing pattern regime of the circuit. Increasing the slow feedback bias evokes slow-loop bistability, leading to bursting behavior. Ultraslow adaptation provides burst termination and controls interburst intervals.

The time constants are set by integrating capacitors: $C_f$, $C_s$, $C_u$, with $\tau_f \ll \tau_s \ll \tau_u$, reproducing the fast–slow–ultraslow hierarchy observed in biological neurons (Mendolia et al., 30 Nov 2025, Ribar et al., 2018). This division is essential for robust phase-plane geometry and bifurcation structure.

4. Analysis and Tuning: Bifurcations, Stability, and Robustness

Operating regimes and bifurcation transitions are analyzed by freezing slow variables and plotting fast, slow, and ultraslow steady-state I–I curves: $$\begin{aligned} I_{app} = \bar I_f - \mathcal S_f(\bar I_f; \bar I_{G_f}), \ I_{app} = 2 \bar I_s - \mathcal S_f(\bar I_s; \bar I_{G_f}) - \mathcal S_s(\bar I_s; \bar I_{G_s}), \ I_{app} = 3 \bar I_u - \mathcal S_f(\bar I_u; \bar I_{G_f}) - \mathcal S_s(\bar I_u; \bar I_{G_s}), \end{aligned}$$ Regions of negative slope (bistability) predict transitions between tonic spiking and bursting.

Parameter tuning involves selecting capacitor ratios ($C_s/C_f$, $C_u/C_s$), adjusting DPI gain through bias currents, and setting comparator thresholds. Uniform scaling of all bias currents yields current-scale invariance, preserving qualitative dynamics across orders-of-magnitude variation. The use of subthreshold exponential MOSFET physics further ensures temperature invariance (Mendolia et al., 30 Nov 2025).

5. Experimental Results and Theoretical Predictions

Experimental validation in 180 nm CMOS prototypes demonstrates:

• Tonic spiking at moderate $I_{G_s}$, bursting when slow-loop bistability emerges.
• Smooth frequency–input (f–I) curves with robust transitions between spiking and bursting regimes.
• Energy consumption per spike ranges from 40–200 pJ/spike, with area and power measurements matching theoretical predictions within 10%.
• Robustness to temperature (spiking frequency increases from $\sim0.5\,$Hz at $5^\circ$C to $25\,$Hz at $45^\circ$C) and to $100\times$ scaling in bias currents, without qualitative change in dynamics (Mendolia et al., 30 Nov 2025, Ribar et al., 2018).

Comparison with SPICE models in other processes, e.g., TSMC $0.35\,\mu$m (Ribar et al., 2018), confirms that the neuromodulatory control scheme—implemented via bias voltage tuning—preserves bursting, spike frequency, amplitude, and operating regime under process and temperature spread.

6. Practical Design, Application, and Scalability

Current-mode neuromodulable neurons utilize a minimal set of modular building blocks (DPI, current-mode sigmoid, low-pass filters), with circuit core sizes as low as $85\,\mu\text{m}^2$ in subthreshold MOSFET implementations and $\approx3800\,\mu\text{m}^2$ in standard 180 nm CMOS (Mendolia et al., 30 Nov 2025, Ribar et al., 2018). The technology supports:

• Power-efficient operation ($\sim3\,\text{nW}$ rest, $\sim10\,\text{nW}$ spike).
• Bandwidth sufficient for biological spiking and bursting diversity ($200$–$500\,\text{Hz}$ spiking, $10$–$50\,\text{Hz}$ bursting).
• Modularity for scalable arrays; layout advantages from repeated use of standard subcircuits.
• Edge computing, central pattern generators (CPGs), and adaptive sensory processing applications where on-chip neuromodulation enables rapid, context-dependent regime switching via a single bias per neuron.

A plausible implication is that such circuits, when embedded in large-scale neuromorphic architectures, directly support robust, energy-efficient computation that is adaptive to both environmental and task-dependent requirements via neuromodulatory control (Mendolia et al., 30 Nov 2025, Ribar et al., 2018, Castaños et al., 2016).