Backpropamine: Silicon Neuromodulable Neurons

• Backpropamine is a term for current-mode neuromodulable silicon neurons that replicate adaptive biological firing dynamics using minimal CMOS circuits.
• The design utilizes differential-pair integrators with fast, slow, and ultraslow time constants to toggle between tonic spiking and bursting behaviors.
• Experimental validations show energy-efficient performance with robust operation across wide temperature and bias variations in 180 nm CMOS implementations.

Current-mode neuromodulable silicon neurons are mixed-signal neuromorphic circuit elements that replicate the robust, adaptable firing dynamics of biological neurons via tunable feedback implemented in subthreshold CMOS technologies and current-mode analog designs. These circuits leverage differential-pair integrators (DPIs), current-mode sigmoidal feedback blocks, and neuromodulatory bias mechanisms to achieve context-sensitive firing patterns such as tonic spiking and bursting, validated both theoretically and experimentally with low-noise, low-power silicon implementations (Mendolia et al., 30 Nov 2025, Ribar et al., 2018, Castaños et al., 2016).

1. Circuit Architecture and CMOS Implementation

Current-mode neuromodulable silicon neurons utilize a minimal analog architecture, executed in standard CMOS processes (e.g., 180 nm, 0.35 μm). The neuron core consists of three integrator subcircuits, each realized by a Differential-Pair Integrator (DPI) with distinct time constants:

• Fast DPI ($I_f$, “membrane”): responds rapidly (τ_f ≈ 1–5 ms), sets spiking dynamics.
• Slow DPI ($I_s$): mediates slow positive feedback for regenerative firing and repolarization (τ_s ≈ 20–50 ms).
• Ultraslow DPI ($I_u$): provides adaptation and burst termination (τ_u ≈ 100–300 ms).

Each path is augmented by a current-mode sigmoid, implemented using comparator-gain blocks with transistor-level subtraction for inactivation. Inactivation is achieved by dynamically reducing the gain bias $I_{G_f}$ and $I_{G_s}$ proportional to the output of the slow and ultraslow DPIs:

$$\begin{aligned} I_{G_f}(t) &= I_{G_f,0} - I_s(t) \ I_{G_s}(t) &= I_{G_s,0} - I_u(t) \end{aligned}$$

This structure ensures robust, analog feedback and adaption analogous to biophysical neuromodulation.

Typical 180 nm CMOS implementations exhibit:

• Area ≈ 3800 μm² per neuron
• Rest power ≈ 3 nW @ 1.8 V, instantaneous spike power ≈ 10 nW
• Energy per spike: 40–200 pJ (rate-dependent, 23–160 Hz)

2. Mathematical and Dynamical Models

The circuit behavior is governed by coupled first-order differential equations with separated timescales:

$$\begin{aligned} \tau_f \frac{dI_f}{dt} &= -I_f + G_f \left[ \mathcal{S}_f(I_f; I_{G_f}(t)) + \mathcal{S}_s(I_s; I_{G_s}(t)) - I_s - I_u + I_{app} \right] \ \tau_s \frac{dI_s}{dt} &= -I_s + G_s \, I_f \ \tau_u \frac{dI_u}{dt} &= -I_u + G_u \, I_f \end{aligned}$$

Where:

• $I_f, I_s, I_u$ are the fast, slow, and ultraslow integrator outputs
• $\mathcal{S}_f$ and $\mathcal{S}_s$ are static current-mode sigmoid functions, determining positive feedback and regenerative gain
• $G_f, G_s, G_u$ are DPI gains, adjustable via bias currents

Neuromodulation enters primarily via the slow-loop gain bias $I_{G_s,0}$, which tunes the system's excitability and initiates transitions between tonic spiking and bursting. Inactivation currents mediated by $I_s$ and $I_u$ dynamically shrink the positive feedback windows, enabling spike and burst accommodation.

3. Neuromodulation Principles and Mechanistic Insights

In direct analogy to physiological neuromodulation—where slow ionic conductances are modulated by chemical neuromodulators—current-mode neuromodulable silicon neurons implement context-sensitive adaptation by tuning the slow and ultraslow feedback via bias currents. Raising $I_{G_s,0}$ deepens the slow-loop bistability, converting tonic spiking into bursting as the neuron accumulates slow feedback ($I_s$). After a burst, ultraslow adaptation ($I_u$) transiently depresses the gain, ensuring return to baseline and reproducible interburst intervals.

Analytically, stability and firing regime transitions are mapped by plotting steady-state “I–I” curves for each feedback path, identifying regions of negative slope (bistability) that predict the onset of spiking, bursting, or quiescence. The transitions between regimes are singularity-structured and correspond to saddle-node and pitchfork bifurcations in the phase-plane geometry (Castaños et al., 2016).

4. Implementation Strategies in CMOS and Discrete Devices

The DPI and current-mode sigmoid subcircuits can be efficiently realized in subthreshold CMOS, weak-inversion MOSFET diff-pairs, and classic bipolar transistor blocks. Key design parameters—capacitance, bias currents, and resistor ratios—scale the dynamic range and time constants over orders of magnitude, enabling operation in pA–nA (energy-optimal for ultra-low-power neuromorphic systems) or μA regimes (for process-robustness).

Design tables specify transistor sizes, capacitor values, and resistor ratios to ensure the predicted mirrored-hysteresis I–V characteristics and robust firing transitions. Bias retuning restores functionality across ±10% process variations and wide temperature ranges. For instance, in MOSFET-based circuits (Ribar et al., 2018), tail currents set tanh gain, input capacitors establish time constants $T_x = 2 v_T C_{T_x} / (\kappa i_{T_x})$, and tuning of bias voltages enables smooth, hardware-calibrated transitions between tonic and bursting firing.

5. Experimental Validation, Performance Metrics, and Robustness

Empirical studies on 180 nm CMOS prototypes demonstrate:

• Tonic spiking frequencies from ≈ 2 Hz up to ≈ 50 Hz as $I_{app}$ increases from 0.1 nA to 1 nA.
• Bursting mode achieved by raising $I_{G_s,0}$, producing bursts of 3–5 spikes with interburst intervals ≈ 200 ms for $I_{app}\approx0.5$ nA.
• Robust scaling: ×100 variation in bias currents and operation over 5–45 °C preserves qualitative firing patterns.
• Measured energy/spike matches theoretical predictions (≈41 pJ at 160 Hz, 217 pJ at 23 Hz); area per neuron consistently ≈3800–4200 μm².

SPICE simulation and hardware results confirm the match between theoretical I–V curve bifurcations and observed firing regime transitions. The mirrored-hysteresis singularity-based design ensures immunity to device mismatch and temperature drift (Castaños et al., 2016).

6. Applications and Design Significance

Current-mode neuromodulable neurons support robust, adaptable, and energy-efficient neuromorphic systems, particularly for edge computing, central pattern generators (CPGs), and adaptive sensory processing. Their modular, bias-controlled neuromodulation enables context-dependent switching (e.g., between tonic and burst encoding) with minimal control—typically a single bias current per neuron. Current-scale invariance and temperature resilience make these architectures suitable for high-yield, large-scale network implementations in practical environments (Mendolia et al., 30 Nov 2025).

This hardware instantiation of neuromodulatory mechanisms establishes a circuit-level foundation for real-time, biophysically realistic neural computation and dynamic regulation of firing patterns for adaptive artificial intelligence systems.