NEURA: Retargetable Compilation for CGRAs

• NEURA is a unified compilation framework that transforms branches, loops, and nested controls into a single dataflow graph using a predicated type system.
• The framework augments each SSA value with a validity predicate, allowing hierarchical control contexts to be embedded directly into data dependencies.
• Experimental results show significant performance and energy gains on both spatial-only and spatio-temporal CGRAs with minimal hardware overhead.

NEURA is a unified and retargetable compilation framework for coarse-grained reconfigurable architectures (CGRAs) that addresses the control-dataflow semantic gap by embedding control contexts into data through a predicated type system. Its central claim is that branches, loops, and nested control structures can be flattened into a single pure dataflow graph when every SSA value carries both a payload and a validity predicate. This enables a kernel representation that is decoupled from a particular CGRA execution model and can be retargeted to spatial-only and spatio-temporal CGRAs, as well as specialized through lightweight rewriting for hardware features such as fused operators and loop-streaming units (Li et al., 5 Apr 2026).

1. Problem formulation and historical context

NEURA is motivated by a longstanding mismatch between the way accelerated kernels are usually represented and the way CGRAs execute them. Real kernels are commonly expressed as a control-dataflow graph (CDFG): arithmetic inside basic blocks is dataflow-like, while branches, loops, and nested structures reside in the control-flow graph (CFG). CGRAs, by contrast, execute statically mapped dataflow graphs in a parallel, data-driven fabric. The resulting incompatibility is framed as a fundamental control-dataflow semantic gap. In practical terms, the computation model of the fabric is well aligned with DFG execution, whereas CFG constructs such as conditionals and loops do not map natively onto the same substrate (Li et al., 5 Apr 2026).

The paper identifies three prior strategies and treats each as incomplete. The first is the external-controller CDFG strategy, in which CFG handling is offloaded to a host CPU or dedicated controller. That approach serializes execution at basic-block or fused-block granularity, introduces communication and reconfiguration bubbles, and leaves inter-block parallelism unexploited. The second is steering control, which physically steers values along preconfigured routes so that control is flattened into data movement. The paper argues that this approach is mainly suited to spatial-only CGRAs; for spatio-temporal systems, dynamic token latencies and route dependence complicate scheduling, and long physical routes can reduce performance. The third is conventional predication, which can express simple branches but not hierarchical control contexts such as nested loops or branches inside loops. In those settings, only the innermost divergence can be predicated, while the enclosing loop structure remains in the CFG and must still be executed in a serialized fashion.

Against this background, NEURA is presented as the first unified solution that represents hierarchical predicate contexts directly inside a pure dataflow graph. The significance of that claim is architectural rather than merely syntactic: if control can be represented as a property of data, then the compiler no longer needs to preserve a separate control layer for nested program structure. A plausible implication is that the boundary between “control handling” and “compute mapping” becomes substantially thinner than in earlier CGRA compilation schemes.

2. Intermediate representations and the predicated type system

NEURA has a two-layer IR design. The first layer, NEURA CDFG IR, is an LLVM-like canonicalization bridge from standard MLIR dialects into a form that preserves explicit control flow while making data dependencies systematic. Its role is to normalize diverse frontends and expose the dependencies that later passes need for predicate propagation. The second layer, NEURA Dataflow IR, is the core contribution: a pure DFG representing the whole kernel without branches.

The novelty of NEURA Dataflow IR lies in its predicated type system. Every SSA value is augmented with a Boolean predicate bit, so a typed value is conceptually a pair $(d,p)$, or equivalently a predicated type $\tau_p$. The predicate states whether the payload is valid on the current execution path. If the predicate is false, the value is nullified, and any consuming operation is guaranteed to have no side effect. The typing rule is given as

$$\frac{\Gamma \vdash d : \tau \quad \Gamma \vdash p : \mathbb{B}}{\Gamma \vdash (d,p) : \tau_p}.$$

The operational semantics makes this design concrete. For predicated computation, two inputs evaluating to $(d_1,p_1)$ and $(d_2,p_2)$ produce a payload computed in the ordinary way, while the output predicate is the conjunction of the input predicates:

$$\frac{\langle v_1, \sigma \rangle \Downarrow \langle(d_1,p_1),\sigma\rangle \quad \langle v_2,\sigma \rangle \Downarrow \langle(d_2,p_2),\sigma\rangle \quad d_{res}=d_1\oplus d_2 \quad p_{res}=p_1\land p_2}{\langle v_1 \bm{\oplus_p} v_2,\sigma\rangle \Downarrow \langle(d_{res},p_{res}),\sigma\rangle}.$$

This conjunction semantics is the mechanism by which hierarchical control contexts are represented: predicates from enclosing scopes accumulate naturally through conjunction. Loads, stores, and returns are similarly predicated, so side effects occur only when the relevant predicates evaluate to true. The paper also introduces three core predicate-management operations. neura.grant_once(val) assigns a one-time true predicate. neura.grant_predicate(val, cond) creates a new predicate from a data condition, with output predicate equal to the conjunction of the incoming value predicate and the condition predicate. neura.phi(...) merges multiple control/data paths by selecting the unique input whose predicate is true and forwarding its payload with a true predicate (Li et al., 5 Apr 2026).

The operation set is organized into four categories:

Category	Examples	Role
Predicated computational ops	arithmetic/logical ops	Compute on predicated values
Predicated state-access ops	load, store, return	Guard side effects by predicates
Predicate-management ops	grant_once, grant_predicate, phi	Create and merge validity
Non-materialized structural ops	neura.reserve, neura.ctrl_mov	Preserve SSA and encode dependencies

The paper additionally defines CGRA-specific fused operations such as neura.muladd, neura.load_indexed, and neura.loop_control, introduced through hardware-specific rewriting passes. This suggests that the IR is deliberately stratified: a small universal predication substrate captures control semantics, while target-specific instructions are layered on later for specialization.

3. Compilation pipeline and flattening of hierarchical control

The frontend accepts C/C++ and MLIR-level inputs including llvm, arith, linalg, and tensor dialects. These are first lowered into NEURA CDFG IR. Preprocessing then canonicalizes the representation. One pass promotes function arguments to explicit neura.constant values in the entry block so that all inputs become SSA-defined values. The critical pass is canonicalize-live-in, which makes inter-basic-block data dependencies explicit (Li et al., 5 Apr 2026).

The paper classifies CFG edges into eight types according to forward or backward direction, branch kind (br or cond_br), and whether values are explicitly passed. Many edges do not explicitly carry values, which obstructs systematic predicate propagation. canonicalize-live-in therefore performs a fixed-point live-in analysis and rewrites blocks so that every control-flow edge explicitly passes the complete live-in set as block arguments. The associated result is stated as Theorem 1: after transformation, every relevant predecessor-to-successor edge explicitly passes the successor’s full live-in set. In compiler terms, this pass converts implicit cross-block dependence into explicit SSA plumbing, thereby creating the conditions under which control-to-data rewriting can be made deterministic.

After live-ins are canonicalized, the compiler applies data predication by converting every SSA type $\tau$ into its predicated counterpart $\tau_p$ and replacing ordinary operations with predicated variants. The final flattening pass, transform-ctrl-to-data-flow, then eliminates branch instructions entirely. For forward edges that carry data, rewriting rules translate control dependencies into data dependencies using predicate-management operations and structural operations. Backward edges are more difficult because naïve flattening can violate SSA by referencing values before their definitions. NEURA addresses this with neura.reserve as a placeholder SSA value and neura.ctrl_mov to create the backward dependency later, thereby preserving SSA while flattening loops and recurrences.

The result is a single DFG for the whole kernel. The significance of this transformation is not merely that branches disappear syntactically, but that instruction-level parallelism can now span regions of the original program that would otherwise have been partitioned into separate basic blocks. This is the mechanism by which NEURA claims to recover inter-block parallelism without reverting to a controller-managed execution model.

4. Retargetability across CGRA execution models

Retargetability is a primary design objective. The IR is described as intentionally close to hardware without being tied to any specific CGRA organization. Existing compute instructions are minimally modified so that they accept predicate bits and compute output predicates by AND-ing incoming predicates. State-access instructions use the conjunction of input predicates as an enable signal, so memory or termination side effects occur only when predicates are true. The paper emphasizes that these changes are low-cost, often amounting to one AND gate per functional unit (Li et al., 5 Apr 2026).

Only three new instructions are required universally: grant_once, grant_predicate, and phi. According to the paper, these are sufficient to express the necessary predicate logic. Because the core representation is a pure DFG, the same kernel can target spatial-only and spatio-temporal CGRAs. The framework can also exploit microarchitectural features through rewriting. Common compute patterns can be fused into target-specific units such as muladd or load_indexed, and generic loop control can be replaced with loop_control on architectures that support loop streaming. The paper further notes that the IR can be transformed into a steering-control representation for compatibility with steering-based architectures such as RipTide.

This notion of retargetability is stronger than source portability alone. It denotes a separation between logical kernel representation and concrete execution model. The base IR remains generic enough to support multiple CGRA families, while specialization is deferred to rewriting passes keyed to the target. A plausible implication is that NEURA treats retargeting as a compiler-internal refinement problem rather than as a front-end recompilation problem.

5. Evaluation methodology and reported results

The evaluation uses two prototype $6\times 6$ CGRA architectures implemented in RTL: NEURA-SO, a spatial-only target, and NEURA-ST, a spatio-temporal target. Both include only the minimal ISA extensions required by the IR. The baselines are Marionette, representing the external-controller CDFG strategy; RipTide, representing steering control; and ICED, representing limited predication. Kernels are drawn from PolyBench, MachSuite, CGRA-Bench, and CHStone, and grouped into machine learning, linear algebra, signal processing, and graph algorithms. Two multi-kernel real applications are also evaluated: a 2-layer GCN and LU decomposition. All systems are normalized to 800 MHz, and the evaluation uses the same mapping algorithm across frameworks to isolate compiler effects (Li et al., 5 Apr 2026).

The reported hardware overhead is modest. Synthesizing the NEURA-enabled architectures incurs 1.89% area overhead for NEURA-SO and 1.39% for NEURA-ST. Performance-wise, NEURA-ST delivers the strongest overall result. Against Marionette, ICED, and RipTide, it achieves geometric mean speedups of $2.20\times$, $\tau_p$0, and $\tau_p$1 respectively on kernel benchmarks. On benchmarks with hierarchical nested control flow, it reaches $\tau_p$2 geometric mean speedup over ICED, reflecting the fact that ICED cannot fully flatten the surrounding loop structure. Relative to RipTide, NEURA-ST is especially advantageous on programs with long data dependencies, where the spatio-temporal model avoids the long static routes that degrade steering-based spatial-only compilation; the paper reports $\tau_p$3 geomean speedup on those cases.

At the application level, NEURA-ST achieves $\tau_p$4 and $\tau_p$5 geometric mean speedup over all baselines on GCN and LU decomposition, respectively, and the $\tau_p$6 geomean application speedup is highlighted as a headline result. It also achieves a $\tau_p$7 geometric mean performance-per-area improvement over Marionette and $\tau_p$8 over ICED.

For spatial-only targets, NEURA-SO is described as competitive rather than dominant. It exceeds RipTide by about 10% in geometric mean performance, improves IPC by 28%, and improves performance per area by 12%. Its geomean energy is only $\tau_p$9 higher than RipTide’s, and the paper notes that on some benchmarks RipTide remains better because of its more specialized merge operation. Scalability experiments show that the same NEURA Dataflow IR runs better on a $$\frac{\Gamma \vdash d : \tau \quad \Gamma \vdash p : \mathbb{B}}{\Gamma \vdash (d,p) : \tau_p}.$$0 than a $$\frac{\Gamma \vdash d : \tau \quad \Gamma \vdash p : \mathbb{B}}{\Gamma \vdash (d,p) : \tau_p}.$$1 fabric, with $$\frac{\Gamma \vdash d : \tau \quad \Gamma \vdash p : \mathbb{B}}{\Gamma \vdash (d,p) : \tau_p}.$$2 geomean speedup, although scaling is not linear because some workloads are limited by dependency chains rather than tile count. A hardware-specialization study reports that hardware-agnostic optimizations such as type alignment and constant folding yield $$\frac{\Gamma \vdash d : \tau \quad \Gamma \vdash p : \mathbb{B}}{\Gamma \vdash (d,p) : \tau_p}.$$3 geomean speedup, adding fused load support raises this to $$\frac{\Gamma \vdash d : \tau \quad \Gamma \vdash p : \mathbb{B}}{\Gamma \vdash (d,p) : \tau_p}.$$4, and adding loop streaming pushes the cumulative gain to $$\frac{\Gamma \vdash d : \tau \quad \Gamma \vdash p : \mathbb{B}}{\Gamma \vdash (d,p) : \tau_p}.$$5.

These results support two claims simultaneously. First, the predicated type system and unified DFG are not merely formal devices; they translate into measurable performance gains when control flow is the dominant obstacle. Second, the base representation remains sufficiently generic that competitive performance can be retained even on targets for which the framework is not maximally specialized.

6. Limitations, tradeoffs, and broader significance

The paper is explicit about its assumptions and limitations. It assumes kernels are available in a form that can be lowered into MLIR and represented as CDFGs, and it currently starts from C/C++ or high-level MLIR dialects. It also assumes a CGRA ISA that can be minimally extended with predicate bits and a small number of new instructions. Automatic selection of the optimal acceleration granularity is not solved: the evaluation instead tries possible granularities and chooses the best one (Li et al., 5 Apr 2026).

A second limitation is the tradeoff between generality and specialization. The base NEURA IR is intentionally generic, which supports portability across different execution models, but this same generality means that a highly specialized low-power architecture such as RipTide can still be better in energy or on certain control patterns. The paper interprets this not as a contradiction but as a design choice: NEURA provides a small, general instruction set as a baseline and relies on hardware-specific rewrites where more specialization is desirable.

The broader significance of NEURA lies in its representational strategy. Its main contribution is not reducible to an isolated compiler pass or a narrowly targeted optimization. Rather, it proposes that control should be represented as data through a predicated type system, so that even hierarchical control flow can be flattened into one DFG without fallback to serialized basic-block execution. In that sense, NEURA redefines what “retargetable” means for CGRA compilation: the same logical kernel representation can be specialized to spatial-only or spatio-temporal fabrics and adapted to architectural features through lightweight rewriting. The framework is open-source and available at https://github.com/coredac/neura, which may facilitate follow-on work on compiler passes, ISA experiments, and CGRA design-space exploration.