NEURA: A Unified and Retargetable Compilation Framework for Coarse-Grained Reconfigurable Architectures

Abstract: Coarse-Grained Reconfigurable Architectures (CGRAs) are a promising and versatile accelerator platform, offering a balance between the performance and efficiency of specialized accelerators and the software programmability. However, their full potential is severely hindered by control flow in accelerated kernels, as the control flow (e.g., loops, branches) is fundamentally incompatible with the parallel, data-driven CGRA fabric. Prior strategies to resolve this mismatch in CGRA kernel acceleration are either inefficient, sacrificing performance for generality, or lack generality due to the difficulty of adapting them across different execution models. Thus, a general and unified solution for efficient CGRA kernel acceleration remains elusive. This paper introduces NEURA, a unified and retargetable compilation framework that systematically resolves the control-dataflow mismatch in CGRAs. NEURA's core innovation is a novel, pure dataflow intermediate representation (IR) built on a predicated type system. In this IR, control contexts are embedded as a predicate within each data, making control an intrinsic property of data. This mechanism enables NEURA to systematically flatten complex control flow into a single unified dataflow graph. This unified representation decouples kernel representation from hardware, empowering NEURA to retarget diverse CGRAs with different execution models and microarchitectural features. When targeted to a high-performance spatio-temporal CGRA, NEURA delivers a 2.20x speedup on kernel benchmarks and up to 2.71x geometric mean speedup on real-world applications over state-of-the-art (SOTA) high-performance baselines. It also provides a competitive solution against the SOTA low-power CGRA when retargeted to a spatial-only CGRA. NEURA is open-source and available at https://github.com/coredac/neura.

• The paper introduces a pure dataflow IR with hierarchical predication that systematically flattens nested control flow into a unified dataflow graph.
• It leverages an MLIR-based transformation pipeline to convert traditional control structures into data dependencies, significantly enhancing parallelism and speedup.
• The framework supports retargetability with minimal hardware modifications, delivering robust performance for both high-performance and low-power CGRA targets.

NEURA: Unified Compilation for Coarse-Grained Reconfigurable Architectures

Motivation and Problem Statement

Coarse-Grained Reconfigurable Architectures (CGRAs) are an emergent class of programmable spatial accelerators, balancing the performance and efficiency of domain-specific architectures with the flexibility of software programmability. The principal obstacle to unleashing their full computational potential is the incongruence between control flow (e.g., loops, branches) and the data-driven, parallel CGRA computation model. This control-dataflow semantic gap manifests as serial execution bottlenecks and limits the parallel exploitation of instruction-level parallelism (ILP) across basic blocks (BBs).

Figure 1: Overview of control and dataflow handling strategies for a nested-loop kernel, illustrating the serialization, steering, limited predication, and NEURA's unified DFG.

Traditional strategies—external controller serialization, steering control flattening, and limited predication—are each fundamentally flawed. External controllers serialize execution at BB or fused-block granularity, suppressing inter-block parallelism. Steering control is essentially limited to spatial-only models and is difficult to generalize to spatio-temporal execution, degrading performance and architectural generality. Existing predicate techniques fail to propagate hierarchical predicates from nested loops and branches, retreating to hybrid approaches that revert to serial execution for complex control structures.

NEURA's Core Contributions

Unified Dataflow Intermediate Representation

NEURA introduces a pure dataflow intermediate representation (IR) built on a predicated type system. The IR augments each value with a predicate bit, making control context an intrinsic property of data. Predicate management operations (e.g., grant_predicate, phi) systematically integrate hierarchical control dependencies into data dependencies, enabling the compiler to flatten any kernel with arbitrary nested control-flow into a single, unified dataflow graph (DFG). This representation is decoupled from hardware, facilitating retargetability across diverse CGRA execution models.

Systematic Flattening Methodology

NEURA's canonicalization and transformation pipeline leverages MLIR infrastructure, progressing through:

• Lowering into NEURA CDFG IR for preprocessing and canonicalization of inter-block data dependencies.
• Lifting all values to predicated types and converting operations to predicated counterparts.
• Deterministic rewriting of CFG edges (forward/backward, branch types) into dataflow dependencies via specialized operations, while strictly preserving SSA form.

  Figure 2: NEURA's compilation pipeline from frontend lowering, CDFG preprocessing, predicated typing, and dataflow flattening to mapping/simulation.

Retargetable Compilation and Hardware Interface

The NEURA Dataflow IR is hardware-conscious and mandates minimal ISA extensions—a predicate bit per operand and three specialized instructions for predicate management. All existing computational and state-access instructions are augmented to propagate predicates, incurring negligible hardware and routing overhead (~1.89% area cost in spatial-only, ~1.39% in spatio-temporal CGRAs).

Figure 3: Sequential transformation of a kernel from MLIR dialects into NEURA Dataflow IR, with stepwise canonicalization and predication.

Hardware-Agnostic and -Specific Optimizations

NEURA integrates optimizations at multiple pipeline stages:

• Canonicalize-cast and fold-constant passes align data types and embed constants directly, eliminating redundant operations and freeing hardware resources.
• Pattern fusion and loop streaming optimizations leverage hardware features (e.g., fused operations, loop streaming FUs), reducing DFG critical paths and improving pipelining.

Experimental Evaluation

High-Performance and Low-Power CGRA Targets

NEURA was evaluated on RTL-prototype CGRAs (NEURA-ST: spatio-temporal, NEURA-SO: spatial-only) and compared to three leading frameworks (Marionette, RipTide, ICED) representing the CDFG, steering control, and limited predication strategies.

Figure 4: Kernel-level speedup comparison across NEURA-ST, Marionette, ICED, and RipTide, with NEURA achieving consistently higher geometric mean speedups.

NEURA-ST consistently outperforms baselines in speedup (2.20× geomean vs. Marionette, 2.24× vs. ICED, 2.42× vs. RipTide), IPC, and performance per area (6.4× over Marionette), and delivers up to 2.71× geomean speedup on real application workloads.

Figure 5: IPC comparison indicating superior exploitation of ILP in NEURA-ST relative to all baselines.

Figure 6: Performance per area (Perf/Area) comparison highlighting NEURA-ST's efficiency.

NEURA-SO achieves competitive performance and energy efficiency in the low-power domain, outperforming RipTide by up to 12% Perf/Area and maintaining only 1.15× geomean energy overhead.

Optimization Impact and Scalability

Hardware-agnostic optimizations (type alignment, constant folding) yield 1.69× geomean speedup; hardware-specific fusions further uplift cumulative speedup to 2.19×. NEURA's IR is scalable: increasing fabric size from 4×4 to 6×6 yields 1.34× geomean speedup, saturating hardware parallelism as expected due to DFG resource constraints.

Theoretical and Practical Implications

NEURA's unified dataflow IR with hierarchical predication fundamentally resolves the control-dataflow semantic gap in CGRA compilation. It enables for the first time systematic flattening of arbitrary nested control constructs into data dependencies, removing serialized execution bottlenecks and facilitating the exploitation of ILP across both intra- and inter-block scopes. The decoupling from execution models and minimal hardware changes underpins broad retargetability and future-proofing for emerging CGRA paradigms, including custom FUs and LLM accelerators.

Practical implications include extensible compiler infrastructure supporting rapid adaptation to new frontends (e.g., PyTorch, tensor dialects), seamless integration of domain-specific hardware features, and flexible acceleration granularity from loop bodies to full kernels. Application-level performance attests to NEURA's capability for holistic workload optimization.

Future Directions

NEURA's extensible IR framework provides the foundation for domain-specific mapping, automated acceleration granularity selection, compositional optimizations for multi-kernel workloads, and integration with next-generation spatial architectures and AI accelerators. Advancing mapping heuristics and incorporating dynamic scheduling models (e.g., temporal pipelining, task-level parallelism) present further avenues for research. Hierarchical predication could be extended for speculative execution and fine-grained synchronizations required in heterogenous spatial compute fabrics.

Conclusion

NEURA establishes a unified, retargetable, and compiler-centric solution for efficiently bridging control flow and dataflow in CGRA programming (2604.04236). Its pure dataflow IR with hierarchical predication enables kernel flattening and exploitation of maximal parallelism across arbitrary control structures. The framework demonstrates robust performance scaling, minimal hardware overhead, and practical extensibility, substantiating its adoption for both high-performance and low-power CGRA accelerator designs.