CGAR: Coarse-Grained Reconfigurable Arrays

• CGAR refers to coarse-grained reconfigurable arrays, a 2D mesh of processing elements that blend programmability with hardware efficiency for diverse applications.
• Advanced compiler and mapping methodologies optimize control and data flow graphs to leverage spatial and temporal parallelism, yielding significant performance gains.
• Integrating hybrid memory systems, precise energy modeling, and adaptive reliability strategies, CGAR designs effectively address power, performance, and lifespan challenges.

Coarse-Grained Reconfigurable Arrays (CGRAs) are a class of reconfigurable hardware acceleration architectures structured as a two-dimensional array of processing elements (PEs), each capable of performing arithmetic and logic operations and communicating with its neighbors via a flexible interconnect. CGRAs bridge the gap between fixed-function hardware accelerators (ASICs/FPGAs) and general-purpose CPUs, offering a favorable trade-off between hardware efficiency, programmability, and flexibility for a wide range of compute- and memory-intensive workloads such as digital signal processing, embedded computation, and graph analytics (Aspros et al., 2 Apr 2025, Wang et al., 4 Aug 2025, Liu et al., 13 Aug 2025). Over the past decade, the scope and depth of CGRA research have expanded to encompass not only architectural innovations but also compiler optimizations, memory models, design-space exploration, and adaptive techniques for performance, energy, reliability, and emerging ML/AI workloads.

1. CGRA Architecture: Principles and Design Space

CGRAs are composed of tightly integrated PEs organized in a 2D mesh or toroidal topology. Each PE typically contains:

• A small ALU,
• A local register file,
• Configuration state that defines per-cycle operation,
• Routing logic for inter-PE communication.

Interconnects may range from simple nearest-neighbor links to more complex switch-boxes, enabling dynamic data routing through the array (Aspros et al., 2 Apr 2025, Wang et al., 4 Aug 2025). The array is controlled by a global program counter (PC) or per-PE instruction memories, enabling explicit scheduling of computation and communication.

The design-space of CGRAs spans multiple axes:

• PE count and topology: grid dimensions, inter-PE connectivity.
• ISA design: set of supported ALU/memory operations.
• Interconnect and bus topology: local versus global, 1-to-M, N-to-M, crossbar, banked memory.
• Time-multiplexing: reuse of physical PEs over multiple time steps, reducing area cost for large kernels.
• Memory hierarchy: SPM, multi-level caches, DMA.
• Configurability: full versus partial runtime reconfiguration.

The flexibility intrinsic to CGRAs underpins their utility but poses significant challenges for efficient resource mapping and accurate performance/power estimation (Aspros et al., 2 Apr 2025, Wang et al., 4 Aug 2025, Liu et al., 13 Aug 2025).

2. Compiler and Mapping Methodologies

State-of-the-art CGRA compilation operates in the spatial and temporal domain, targeting effective mapping of applications onto the CGRA mesh. Traditional flows prioritize mapping single-dataflow graphs (DFGs) representing innermost kernel loops, maximizing spatial parallelism via modulo scheduling but typically delegating control-flow management (if-else, loops) to the host or extra hardware (Wang et al., 4 Aug 2025).

Recent approaches extend compilation to arbitrary control-dataflow graphs (CDFGs), leveraging intermediate representations such as MLIR. Key innovations include:

• CFG simplification: horizontal and vertical merges, reducing number of mapped blocks and removing redundant jumps.
• IR-level liveness analysis: optimizing register usage (internal vs. external) across basic blocks for value propagation.
• ILP-based scheduling: per-block, with constraints on PE assignment, time slots, routing, liveness, and memory orderings.
• Modulo-scheduled loop adaption: decomposing kernels into II-sized basic blocks to recover loop-level parallelism even under PC-driven control (Wang et al., 4 Aug 2025).

These advancements enable hardware-agnostic, software-only flows capable of compiling complex applications with arbitrary control flow, achieving up to 2.1× speedup over prior approaches without requiring dedicated control hardware (Wang et al., 4 Aug 2025).

3. Early Performance and Power Modeling

The CGRA design space is vast, requiring efficient exploration tools to avoid exhaustive, time-prohibitive RTL synthesis. A behavioral simulator layered atop a flexible characterization framework enables rapid kernel execution, providing instantaneous energy and latency estimates based on per-PE, per-instruction characterization, memory stalls, idle costs, and interconnect effects (Aspros et al., 2 Apr 2025).

The key modeling equations include:

• Total latency: sum over clock cycles as the simulation advances.
• Per-cycle power: sum of operational, idle, and switching power for all PEs.
• Total energy: sum of per-cycle power over latency.
• Breakdown by instruction: power and latency attribution per micro-operation, incorporating memory and bus contention.

Progressively richer characterization (adding operation-specific, idle, and switching overheads) achieves sub-1% latency error and ≈10% energy error compared with full post-synthesis results for key mapping studies (e.g., MiBench, convolutions), enabling rapid pruning of suboptimal software mappings or hardware topologies (Aspros et al., 2 Apr 2025).

4. Memory System Innovations: Addressing Irregularity

CGRAs' efficacy is often constrained by memory-bound workloads, particularly for irregular access patterns as encountered in graph analytics or unstructured compute (Liu et al., 13 Aug 2025). While traditional models rely upon a monolithic Scratchpad Memory (SPM), practical workloads often exceed SPM size or create unpredictable access streams.

Recent work proposes a hybrid SPM+multi-level cache system, with per-crossbar L1 caches and shared, non-inclusive L2. Key mechanisms include:

• Runahead execution: upon L1 miss, state is checkpointed, computation proceeds using dummy values, and new loads are issued for prefetch. Execution resumes with correct data upon miss resolution.
• Cache reconfiguration: dynamic allocation of associativity and line size to L1 caches via permission registers, maximizing hit rates.
• Analytical modeling: utilization and speedup equations express fraction of time hidden by runahead and effective storage requirements.

Empirically, this approach reduces required storage to 1.27% of the equivalent SPM-only design and yields compounded speedups (3.04× runahead plus 6.02% from cache reconfiguration), with area overhead under 15% for an 8×8 mesh (Liu et al., 13 Aug 2025).

5. Reliability and Aging Mitigation

Device-level reliability in CGRAs is increasingly critical due to negative bias temperature instability (NBTI), which accelerates delay degradation in highly-utilized CMOS FUs. An application-to-CGRA allocation strategy, utilizing dynamic spatial movement of mapped configurations across the fabric, balances FU utilization and substantially extends array lifetime (Brandalero et al., 2020).

This approach employs novel reconfiguration logic—including per-column multiplexer chains and barrel shifters—to shift configurations in both dimensions, ensuring uniform stress distribution. Simulation results on MiBench benchmarks report:

• Max FU utilization reduction from ~98% to ~12–41% (depending on array size and configuration).
• Lifetime extensions of 2.2×–8× versus static mapping.
• Area impact under 5%, with negligible performance penalty (Brandalero et al., 2020).

6. Applications Beyond Hardware: CGAR in Learning Systems

The acronym "CGAR" also denotes algorithmic and training methodologies outside of hardware, notably:

• Critic Guided Action Redistribution in reinforcement learning (Huang et al., 2022): augments actor-critic algorithms by resampling actions from a softmax-weighted candidate set according to the critic’s $Q$-values, producing sample efficiency gains and improved returns in MuJoCo benchmark environments, with 10–30% fewer interactions needed to match SAC baseline performance.
• Curriculum Guided Adaptive Recursion for recursive reasoning models (Qasim et al., 11 Nov 2025): applies architectural-deepening curriculum (progressive increase of recursion depth) plus recursion-aware loss weighting, accelerating training of transformer-based solvers (e.g., Sudoku) by 1.71× with negligible drop in accuracy. Ablation shows a rare Pareto improvement (faster and slightly better) when employing curriculum alone.

While the initialism "CGAR" was coined independently in these contexts, both approaches use it to denote a regime where guidance or adaptivity drives improved sample or computational efficiency beyond naive baselines.

7. Summary of Recent Advances and Open Challenges

The CGRA ecosystem—spanning hardware, compilers, architectural modeling, and adaptive algorithms—has undergone rapid innovation. Current practice encompasses:

• Behaviorally-accurate, characterized hardware and workloads for early DSE and accurate pre-silicon estimation (Aspros et al., 2 Apr 2025).
• Formalized compiler frameworks using MLIR, CFG simplification, ILP/SAT mapping, and liveness-driven value placement for robust support of arbitrary control/data flow (Wang et al., 4 Aug 2025).
• Hybrid SPM/cache memory subsystems, aggressive prefetch and runahead mechanisms, and dynamic associativity management to address memory-side bottlenecks (Liu et al., 13 Aug 2025).
• Active NBTI mitigation and utilization-aware mapping schemes, achieving multi-fold lifetime extension with minimal overhead (Brandalero et al., 2020).
• Algorithmic innovations leveraging critic-driven policy refinement in RL and recursively adaptive curriculum in deep learning, each producing sample or wallclock efficiency improvements under the CGAR acronym (Huang et al., 2022, Qasim et al., 11 Nov 2025).

Persisting challenges include automating cross-layer co-design (joint mapping of algorithm, compiler, architecture, and memory), fully integrating real-time reliability monitoring for adaptive wear-leveling, and extending curriculum or guidance-based techniques to broader ML and system domains. A plausible implication is that cross-disciplinary "CGAR" methodologies will proliferate as the field continues to converge upon scalable, reliable, and adaptive compute fabrics for emerging workload classes.