Loihi 2 Architecture Overview

• Loihi 2 is Intel’s second-generation many-core neuromorphic processor that uses digital, clockless cores and programmable neuron models for event-driven computations.
• It employs an asynchronous 2D mesh interconnect and flexible microcode to support diverse spiking neural network and signal processing tasks.
• Performance gains such as up to 30× energy-delay product reduction and scalable real-time inference enable efficient large-scale, bio-realistic simulations.

Loihi 2 is Intel’s second-generation, fully digital, many-core neuromorphic research processor, designed to support general-purpose event-driven spiking neural network (SNN) computation. It advances architectural principles of stateful, programmable neuron models, asynchronous event-driven communication, and local on-chip learning. The architecture is tailored to enable high-efficiency, low-latency implementations of both bio-inspired and signal processing algorithms such as convolutional networks, spectral transforms, and large-scale connectome simulations. Loihi 2 incorporates innovations in neuron model flexibility, microprogramming, graded (integer-valued) spikes, and network-on-chip organization, yielding major gains in energy-delay product (EDP) and throughput across diverse spiking workloads (Shrestha et al., 2023).

1. System-Level Organization and Core Microarchitecture

Loihi 2 is fabricated in a 10 nm FinFET process and features a two-dimensional mesh array of neuromorphic cores (also referred to as "tiles" or "neurocores"), with up to 128 cores per chip depending on configuration (Shrestha et al., 2023, Isik et al., 28 Aug 2024, Wang et al., 22 Aug 2025). Each core is globally clock-less and locally synchronous, communicating solely via a fully asynchronous, deterministic 2D mesh interconnect for Address-Event Representation (AER) packet transport. The principal architectural blocks are as follows:

Block	Functionality	Key Parameters
Neuromorphic Core	Programmable neuron/synapse pipelines, local multi-bank SRAM for state/weights/microcode	1024 neurons, 16,384 synapses per core (Shrestha et al., 2023)
Mesh Router	4-port (N/S/E/W) asynchronous, XY-routing, 32-bit event packet forwarding	4-phase handshake per hop
Synaptic Engine	Weight-accumulate pipeline, microcoded; 9-bit signed or 12-bit unsigned per weight
Microcode Store	Instruction memory for neuron and synapse routines, RISC-like custom ISA	∼8 kB per core
Power Domains	Tile-level power-gating, per-engine clock-gating
On-Chip DRAM/Flash	Bulk state, programmable tables

Each core's neuron engine consists of 1024 programmable, stateful compartments (multi-register), supported by 16,384-weight synaptic memory. Microprogrammed neuron and synapse update rules run on local instruction stores, supporting both arithmetic and logic, including conditionals and shifts. The mesh network routes 32-bit events, including graded integer payloads, with each hop performing a local four-phase handshake (Shrestha et al., 2023, Isik et al., 28 Aug 2024).

The hierarchical memory system comprises per-core SRAM banks for neuron state, synaptic weights, and microcode, while a tile-shared DRAM interface provides off-chip storage. Power domains are fine-grained, allowing per-tile (and per-engine) gating for energy proportionality.

2. Neuron and Synapse Model Programmability

Loihi 2 generalizes neuron and synapse dynamics beyond first-generation (LIF-only) designs, primarily through microcoded, programmable models. Three principal neuron types are natively supported at the low level:

• Sigma-Delta Encapsulation Neuron (Integer-valued sigma–delta loop):

$$u[t] = \alpha\,u[t-1] + x[t] - \beta\,s[t-1],\quad s[t]= \begin{cases} 0, & u[t] < \theta \ \left\lfloor \tfrac{u[t]}{\theta} \right\rfloor, & u[t]\ge\theta \end{cases}, \quad u[t] \leftarrow u[t] - \theta s[t]$$

Here, $u[t]$ is membrane potential, $x[t]$ is weighted input, $s[t]\in\mathbb{Z}$ is an integer spike, $\alpha,\beta \in (0,1)$ are leakage coefficients, $\theta$ is the threshold. These neurons enable compression of multiple spike quanta per event and low-bandwidth signaling (Shrestha et al., 2023, Stewart et al., 3 Dec 2025).

• Resonate-and-Fire (Discrete Izhikevich) Neuron:

$$\begin{cases} v[t] = v[t-1] + \Delta t (a v[t-1] - b w[t-1] + I[t]) \ w[t] = w[t-1] + \Delta t (c v[t-1] - d w[t-1]) \end{cases},\quad \text{if } v[t] \ge v_{th}: v[t] \gets c_r, w[t] \gets w[t]+d_r, s[t]\gets 1$$

Here, $v$, $w$ are neuron state variables, $a$, $b$, $c$, $d$ are programmable, $\Delta t$ is the time step, $I[t]$ is input current. This form allows direct hardware support for dynamics such as bursting, chattering, and subthreshold resonance, relevant in bio-realistic SNNs (Shrestha et al., 2023, Uludağ et al., 2023).

• Integer Spike Synapse:

Arrival of an integer-valued spike $s_{in}[t]$ at a synapse with weight $W$ updates post-synaptic state $y[t]$ as $y[t] = y[t] + W\,s_{in}[t]$. If $y[t]$ crosses threshold $\Theta$, $k = \lfloor y[t]/\Theta\rfloor$, then $k$ spikes are delivered; $y[t] \gets y[t] - k\Theta$. This supports efficient event compression and transmission (Shrestha et al., 2023).

Microcode ISAs allow user-defined update rules for both neuron and synapse engines, supporting arithmetic/logical/conditional operations (∼16–32 instructions typical). Learning rules (e.g., STDP, reward-modulated plasticity) can be encoded similarly, and both additive and multiply–accumulate learning are expressible at the synaptic microcode level (Shrestha et al., 2023).

3. Event-Driven Routing and Mesh Network

Loihi 2’s connectivity is mediated by a fully asynchronous 2D mesh interconnect, ensuring event-driven system behavior without a global clock (Shrestha et al., 2023, Isik et al., 28 Aug 2024). Each tile communicates via four directional router links (N/S/E/W), with each hop carrying out a four-phase handshake for deterministic, deadlock-free XY routing.

All spikes, including integer-valued or graded events, are packetized as 32-bit AER packets with fields:

• DestTileX (3 bits)
• DestTileY (3 bits)
• CoreID (4 bits)
• NeuronID (10 bits)
• Value (12 bits)

Upon arrival at a destination core, packets are placed into small input FIFOs. The synapse engine microcode accumulates weighted sums from inbound events, after which the neuron engine executes the update rule in microcode. The event network supports broadcast, multicast, and programmable fan-out patterns. This infrastructure is directly relevant for mapping irregular, sparse, or large-scale biological circuits, as demonstrated in whole-brain Drosophila simulations (Wang et al., 22 Aug 2025).

4. Programmability, Memory Model, and On-Chip Learning

Loihi 2 exposes a high degree of programmability for researchers:

• All neuron and synapse parameters (e.g., $a$, $b$, $c$, $d$, $\alpha$, $\beta$, $\theta$) are configured via the NxSDK API and loaded into per-core SRAM before runtime. Microcode can be user-authored per core to implement custom neuron or synapse behaviors (Shrestha et al., 2023, Uludağ et al., 2023).
• Core memory is partitioned into banks for neuron state, synaptic weights (9/12 bits typical per weight), and instruction storage (∼8 kB per core).
• On-chip learning is supported via a programmable microcode engine for spike-timing-dependent plasticity (STDP), additive/multiplicative forms, and reward-based rules. All learning rules operate by atomically reading pre/post spike timestamps and updating weight registers (Shrestha et al., 2023, Isik et al., 28 Aug 2024).

The design supports high memory locality (synaptic memory is directly coupled to neuron engines) and customizable precision (fixed-point, integer). This enables efficient mapping of both dense and extremely sparse, irregular graphs found in biological connectomes, with out-of-core management handled at the stack level (e.g., 128 kB per core for synaptic and neuron state, up to 120–128 cores per chip, as used in multi-chip stacks for whole-brain connectomics (Wang et al., 22 Aug 2025)).

5. Advances over Loihi 1 and Key Architectural Innovations

Loihi 2 delivers several core advancements over the original Loihi 1 architecture (Shrestha et al., 2023, Stewart et al., 3 Dec 2025):

• Programmable Microcode: Arbitrary neuron and synapse programs, including full resonate-and-fire, sigma-delta spiking, and custom logic, replacing Loihi 1’s limited LIF-centric instruction set.
• Graded, Integer-Valued Spikes: Integer-valued spike payloads up to 24 bits (vs. strictly binary events in Loihi 1), supporting event compression and bandwidth reduction.
• Memory/Learning Enhancements: Increased per-core neuron count (1024+) and synapse memory (16,384+ entries per core), more extensive state/register support, and improved, programmable learning engine.
• Event-Driven Mesh: Asynchronous mesh, finer-grain, per-tile power gating, and per-engine clock gating, supporting energy-proportional operation.
• Native Support for Convolutional/Feed-Forward Topologies: Optimizations for convolutional computations in microcode/hardware pipelines, as required for feed-forward SNNs.

These modifications are motivated by the need for more diverse and complex neuron dynamics, event-compressed signaling, and efficient mapping of audio/video/signal processing tasks (Shrestha et al., 2023).

6. Performance Metrics and Comparative Analysis

Loihi 2 achieves major gains in efficiency and latency:

• Energy-Delay Product (EDP):
  • 15×–30× improvement over NVIDIA Jetson Xavier NX for 3×3 convolutional layers (feed-forward SNNs for video tasks).
  • 20× reduction in EDP for audio spectrogram transforms using resonate-and-fire neurons, compared to DSPs.
• Absolute Power:
  • <50 mW to sustain 100 Hz full-resolution video throughput (cf. ∼2 W on GPU).
• Latency and Inference Rate:
  • 2–4× lower energy and 5–10× lower latency per inference relative to state-of-the-art GPU solutions for small-batch video/audio.
  • For robotics control pipelines (converted from RL-trained ANNs), throughput >450 inferences/s, with 0.054–0.056 mJ·s EDP, compared to ∼1.1 mJ·s on GPU (Stewart et al., 3 Dec 2025).
• Event Energy:
  • Per spike event cost reported to be as low as 10 pJ, with total inference energy per time step in bio-realistic SNNs on the order of microjoules (Uludağ et al., 2023, Isik et al., 28 Aug 2024).
• Scalability:
  • The entire Drosophila brain connectome (140K neurons, 50M synapses) mapped to 12 chips (1440 cores total), with single-chip practical fan-in after compression up to ≈165, and wall-clock simulation rates 100–350× faster than optimized CPU simulators for sparse workloads (Wang et al., 22 Aug 2025).
  • Multi-chip stacking (up to 1,152 chips) supports billion-neuron scale inference (Abreu et al., 12 Feb 2025).

These improvements are realized via asynchronous event processing, spike traffic compression (via integer spikes), energy-proportional power domains, and fusion of signal-processing primitives directly into neuron microcode.

7. Architectural Trade-offs and Design Limitations

• Fixed-point and integer precision (typically 8–16 bits for weights and 24 bits for state) trade off dynamic range for energy efficiency (Isik et al., 28 Aug 2024, Uludağ et al., 2023).
• Single-chip core counts cap per-chip network size; scaling to larger graphs involves multi-chip, memory-aware partitioning and routing (Wang et al., 22 Aug 2025).
• Event-driven throughput is outstanding at modest spike rates but can be challenged by high-density traffic, which places pressure on mesh router buffers and end-to-end latency.
• Programming flexibility via microcode comes at the cost of increased mapping and verification complexity, as standard deep learning frameworks require customized toolchains for SNN compilation and microcode generation (Shrestha et al., 2023, Isik et al., 28 Aug 2024).

A plausible implication is that Loihi 2’s flexible, programmable microarchitecture enables practical exploration of mixed-complexity SNNs—combining basic LIF neurons in bulk with a minority of more elaborate, bio-realistic compartments—while retaining real-time performance and low power operation (Uludağ et al., 2023). As software toolchains evolve, deployment of hybrid models and larger graphs is likely to become more routine.