Monolithic 3D-Stackable DRAM

• Mono3D DRAM is a monolithically integrated 3D stackable memory that reorganizes cell arrays and peripheral logic across vertically connected tiers to reduce latency and boost internal bandwidth.
• It exploits subarray reorganization, deep memory stacking, and fine-pitch hybrid bonding to create dense vertical connectivity, enabling efficient near-memory processing and tiered latency management.
• Design optimizations balance sensing margins, thermal budgets, and manufacturing constraints while achieving significant reductions in power consumption, area, and read/write energy compared to conventional 2D DRAM.

Monolithic 3D-Stackable DRAM (Mono3D DRAM) denotes a class of DRAM and DRAM-like memories in which vertical integration is treated as a first-class circuit and architectural variable rather than as a packaging afterthought. In the recent literature, the term covers at least three closely related directions: subarray-level reorganization of conventional 1T1C DRAM using monolithic inter-tier connectivity; very-deep DRAM stacks coupled to a logic die through fine-pitch hybrid bonding and exploited as a compute-capable substrate; and adjacent dynamic BEOL memories, such as gain-cell eDRAM-like arrays, that are monolithically stackable but are not classical commodity DRAM (Huang et al., 2020, Lee et al., 12 Mar 2026, Waqar et al., 8 Mar 2025). Across these directions, the recurring premise is that dense vertical connectivity can shorten critical access paths, expose much higher internal bandwidth than TSV-based stacks, and create new placement, routing, and scheduling opportunities, but only under strict constraints imposed by sensing margin, thermal budget, routing congestion, and manufacturing complexity.

1. Conceptual scope and distinguishing features

Mono3D DRAM is distinct from both conventional planar DDR-class DRAM and TSV-stacked memories such as HBM. In coarse-grained monolithic 3D DRAM, the objective is not merely to stack completed dies, but to reorganize the internals of a DRAM die itself by redistributing cell arrays, sense amplifiers, and peripheral logic across tiers connected by monolithic interlayer vias. One foundational study quantified this distinction by contrasting MIV dimensions of about $50 \text{ nm} \times 100 \text{ nm}$ with TSV dimensions of about $$1\text{–}3\,\mu\text{m} \times 10\text{–}30\,\mu\text{m}$$, arguing that the resulting vertical interconnect density changes the latency–area design space inside the DRAM die rather than only at the package boundary (Huang et al., 2020).

A second strand treats Mono3D DRAM as a deep memory stack with a bottom logic die and a memory die or memory stack above it, interconnected through Cu–Cu hybrid bonding. In this framing, the central advantage is not host-visible bandwidth alone, because the off-stack interface can remain HBM-like, but the much larger internal bandwidth between memory and logic. Stratum, for example, describes hybrid bonding pitch as $1\,\mu\text{m}$ and HBM TSV pitch as $10\,\mu\text{m}$, and uses the resulting fine-grained connectivity to justify near-memory processing on a dedicated logic die rather than inside DRAM mats (Pan et al., 6 Oct 2025).

The literature also uses the broader Mono3D vocabulary for dynamic memories that are not conventional 1T1C DRAM. The AOS 2T gain-cell work is explicit on this point: it studies a capacitorless, non-destructive-read, gain-cell eDRAM-like memory for LLCs, not a direct replacement for commodity off-chip DRAM. This suggests that “Mono3D DRAM” is best treated as a design space whose members share monolithic vertical integration and charge-based storage, but not necessarily identical device physics, peripheral circuits, or system roles (Waqar et al., 8 Mar 2025).

2. Physical organizations and device assumptions

Direct 1T1C Mono3D DRAM proposals already show substantial diversity in physical organization. A coarse-grained approach places DRAM cell arrays, local bitlines, and local wordlines on a top tier, while moving sense amplifiers, precharge units, write drivers, SA I/O, local wordline drivers, and address decoders to a bottom tier. The tier assignment is motivated by asymmetric degradation: the top tier suffers degraded transistor performance, while the bottom tier suffers degraded interconnect performance because tungsten replaces copper, so the array is placed where interconnect sensitivity dominates and the logic is placed where transistor performance matters more (Huang et al., 2020).

A more aggressive realization is the CMOS-Bonded-Array (CBA) organization. Here a stacked 1T1C vertical DRAM array is bonded to a CMOS periphery wafer, with BLSA, row decoder, drivers, internal I/O, and page latch/buffer in the overlying CMOS layer, while selectors for BL/WL multiplexing are integrated on top of the cell in the BEOL region. The optimized layout uses $8$ BLs per strap and $16$ WLs per strap, line-type cell isolation, $Y$-pitch $= 100$ nm, and a unified storage capacitance of $C_s = 4$ fF. The access device can be either epitaxial Si or AOS calibrated to W-doped In$_2$O$$1\text{–}3\,\mu\text{m} \times 10\text{–}30\,\mu\text{m}$$0, while the selector itself is an IGO device adopted for its drivability, compact footprint, and BEOL compatibility (Lee et al., 12 Mar 2026).

System-oriented Mono3D DRAM models assume far deeper stacks. Both Stratum and GenDRAM use a 32 GB, 1024-layer memory organization with 16 channels per chip, 64-bit data I/O per channel, 16 banks per channel, and 8 internal latency tiers of 4 GB each. In GenDRAM this memory is paired with a 7 nm logic die containing 32 processing units at 1 GHz, while the host-facing interface remains 1024 bits at 6.4 Gbps/pin, explicitly shifting emphasis from external I/O to the stack’s far larger internal bandwidth (Lu et al., 27 Feb 2026).

3. Access-path optimization and the latency–area problem

The architectural case for Mono3D DRAM begins with a classical DRAM problem: reducing latency by shortening local bitlines generally worsens area efficiency because it requires more sense amplifiers, more subarrays, and often longer global bitlines. A foundational study quantified this with a 1 Gb, 8-bank DDR4-derived organization in which the baseline DDR4-512 design used 512 cells per local bitline, $$1\text{–}3\,\mu\text{m} \times 10\text{–}30\,\mu\text{m}$$1, $$1\text{–}3\,\mu\text{m} \times 10\text{–}30\,\mu\text{m}$$2, and a bank area of $$1\text{–}3\,\mu\text{m} \times 10\text{–}30\,\mu\text{m}$$3. The corresponding M3D-512 design kept $$1\text{–}3\,\mu\text{m} \times 10\text{–}30\,\mu\text{m}$$4 but reduced $$1\text{–}3\,\mu\text{m} \times 10\text{–}30\,\mu\text{m}$$5 to $$1\text{–}3\,\mu\text{m} \times 10\text{–}30\,\mu\text{m}$$6 by moving SA, precharge, and write-driver footprint beneath the array. The more aggressive M3D-128 design used $$1\text{–}3\,\mu\text{m} \times 10\text{–}30\,\mu\text{m}$$7 cells per local bitline, $$1\text{–}3\,\mu\text{m} \times 10\text{–}30\,\mu\text{m}$$8, $$1\text{–}3\,\mu\text{m} \times 10\text{–}30\,\mu\text{m}$$9, $1\,\mu\text{m}$0 ns, $1\,\mu\text{m}$1 ns, $1\,\mu\text{m}$2 ns, $1\,\mu\text{m}$3 ns, and a bank area of $1\,\mu\text{m}$4. At system level, the paper reported up to $1\,\mu\text{m}$5 lower average access latency, up to $1\,\mu\text{m}$6 lower power, up to $1\,\mu\text{m}$7 lower EDP, and up to $1\,\mu\text{m}$8 less DRAM die area than conventional 2D DDR4 (Huang et al., 2020).

This argument becomes stronger when routing and bonding constraints are modeled explicitly. The CBA study shows that direct BLSA connection or core MUX routing requires prohibitively tight HCB pitch—$1\,\mu\text{m}$9 for Si and $10\,\mu\text{m}$0 for AOS—whereas simple BL strapping relaxes the pitch but inflates effective $10\,\mu\text{m}$1 and degrades sensing. The proposed BL selector + strap architecture preserves the relaxed HCB pitch of $10\,\mu\text{m}$2 for Si and $10\,\mu\text{m}$3 for AOS while reducing effective $10\,\mu\text{m}$4 to 6.6 fF including bonding parasitics, compared with 20 fF for D1b. The resulting initial sense margins are 130 mV for Si and 189 mV for AOS, versus 54 mV for D1b; at a target density of $10\,\mu\text{m}$5, the Si case remains functional with 70 mV margin. Under this co-optimized regime the design reaches $10\,\mu\text{m}$6, corresponding to about $10\,\mu\text{m}$7 density scaling over D1b 2D DRAM, with 137 layers for Si or 87 layers for AOS, nominal $10\,\mu\text{m}$8 below 10.9 ns and 10.5 ns respectively, and a 60% reduction in read/write energy (Lee et al., 12 Mar 2026).

A key implication is that Mono3D DRAM scaling is not determined by cell stacking alone. The feasible operating point is jointly set by access-path length, bonding pitch, effective bitline capacitance, and the ability to preserve sense margin under those parasitics.

4. Tiered latency as an architectural resource

Very-deep Mono3D DRAM introduces a property that planar DRAM and TSV-stacked HBM do not usually expose so explicitly: layer-dependent latency along the $10\,\mu\text{m}$9-dimension. In both Stratum and GenDRAM, wordlines are routed in staircase structures, so deeper layers incur longer RC delay. The resulting 1024-layer stack is divided into 8 timing tiers with

$8$0

with $8$1 ns, $8$2 ns, and $8$3. Stratum summarizes the consequence as a fastest tier that is $8$4 faster than the slowest tier, while GenDRAM reports the fastest tier at approximately 34.56 ns row-cycle latency and the slowest at about 55.15 ns (Pan et al., 6 Oct 2025, Lu et al., 27 Feb 2026).

GenDRAM exploits this heterogeneity directly. It couples 32 PUs in a 1:1 fashion with 32 bank-groups, gives each PU a dedicated 1024-bit I/O into its vertically aligned bank-group, and partitions the logic into 8 Search PUs and 24 Compute PUs. The target workloads are unified as semiring-style DP updates,

$8$5

with APSP using $8$6 and sequence alignment using $8$7. Tier-aware data placement pins the genomics pointer table and candidate location table—together about 17 GB—to Tier 0, while modulo-based interleaving spreads tiles across the 32 PU/bank-group targets. Relative to a naive all-data-in-slowest-tier baseline, this mapping yields about $8$8 speedup and recovers nearly 98% of an idealized all-data-in-Tier-0 upper bound of $8$9. End-to-end, the platform reports over $16$0 speedup over a state-of-the-art GPU system on APSP and over $16$1 on the full genomics pipeline (Lu et al., 27 Feb 2026).

Stratum applies the same physical phenomenon to MoE serving. It places hot expert weights in faster tiers, cold experts in slower tiers, KV cache in intermediate-speed memory, and non-NMP data in the slowest tier. The tiering table in each PE’s local memory controller dynamically translates row addresses to memory-tier identifiers, and expert swaps are performed entirely within Mono3D DRAM using a row-swap buffer. Against a no-tiering variant, tiering plus data mapping improves decoding throughput by averages of $16$2 for OLMoE, $16$3 for Mixtral, $16$4 for Qwen2.5, and $16$5 for Llama-4; the full system achieves up to $16$6 better decoding throughput and $16$7 better energy efficiency relative to GPU baselines (Pan et al., 6 Oct 2025).

Taken together, these results suggest that in Mono3D DRAM the vertical latency gradient is not merely a scaling penalty. It can become an internal memory hierarchy, provided that placement, scheduling, and logic-to-memory attachment are co-designed around it.

5. Reliability, thermal density, and manufacturability

Reliability in Mono3D DRAM differs materially from reliability in planar DRAM. A TCAD study of monolithic 3D-stackable 1T1C DRAM shows that classical charge-migration row hammer is substantially mitigated because the shared bulk path present in 2D DRAM is removed. In the 2D saddle-fin buried-gate reference, victim storage-node voltage loss is $16$8 mV/cycle and the corresponding row-hammer threshold is about 1,120 cycles. In the 3D mini-array without impact ionization, the per-cycle voltage drop is 0.05 mV/cycle for Case 1 ($16$9), 0.01 mV/cycle for Case 2 ($Y$0), and 0.006 mV/cycle for Case 3 ($Y$1), with approximate thresholds of 16.8k, 100.8k, and 86.4k cycles, respectively. However, once impact ionization is enabled, the floating body of the silicon access transistor amplifies vertical capacitive coupling, and the vertically adjacent Case 2 threshold falls to about 11.3k cycles. The same study identifies thinner body, lower doping concentration, and higher gate work function as the preferred mitigation direction, with only a 3.9% change in on-current from Case 3 to Case 5 (Cho et al., 1 Nov 2025).

Thermal and area overheads remain equally central. GenDRAM reports a 105 mm$Y$2 logic die with peak power 31.22 W, estimates around $Y$3 peak power density, and uses thermal risk to justify limiting each PU to 16 PEs rather than 32 or 64. It also reports that PHY plus interfaces occupy about 58% of die area, with the PHY alone at 36.2%, making dense memory coupling rather than arithmetic the dominant area cost (Lu et al., 27 Feb 2026). Stratum, operating at a larger system scale, reports that each Mono3D DRAM die can consume about 104 W at full 30.34 TB/s internal bandwidth, with a logic-die power cap of about 45 W per chip and a total peak stack power of 144.53 W (Pan et al., 6 Oct 2025).

Manufacturing assumptions are similarly stringent. The gain-cell LLC work emphasizes that BEOL-compatible M3D integration requires a low thermal budget below $Y$4, which excludes conventional silicon CMOS processing and motivates AOS, 2D materials, or CNTs; AOS is described as especially attractive because it can be processed below $Y$5 (Waqar et al., 8 Mar 2025). The CBA study, meanwhile, makes clear that large-scale viability is bounded by hybrid bonding precision, selector quality, routing congestion, and sense-margin preservation under disturb mechanisms such as FBE and RH, not by cell demonstration alone (Lee et al., 12 Mar 2026).

6. Adjacent monolithic memories and broader system implications

Not all monolithically stackable dynamic memories are conventional DRAM, and this distinction matters. The AOS 2T-GC LLC work studies W-doped amorphous indium oxide gain-cell memory in which charge is stored on the gate capacitance of the read transistor rather than in a dedicated 1T1C capacitor. At 7 nm, the benchmarked DG IWO 2T-GC cell has area $Y$6, retention 315 ms, and write latency 122 ps; at 3 nm, the CAA IWO 2T-GC cell has area $Y$7, retention 251 ms, and write latency 421 ps. The paper reports refresh energy of around 0.04% of total macro energy, compared with about 13% for 1T1C eDRAM in the studied setup, and shows that a 4-tier 256 MB IWO 2T-GC cache occupies $Y$8, corresponding to $Y$9 higher bit density than SRAM and $= 100$0 over eDRAM. It therefore belongs to the Mono3D landscape as a dynamic, monolithically stackable cache memory, but not as a classical DRAM main-memory replacement (Waqar et al., 8 Mar 2025).

At the processor level, monolithic memory integration also changes system bottlenecks. RevaMp3D is not a DRAM paper—it uses 64 layers of RRAM as main memory—but it shows what happens when memory becomes on-chip, very wide, and very fast: the dominant bottlenecks shift from main memory to the processor core and cache hierarchy. Its M3D baseline assumes up to 16 TB/s memory bandwidth and 5 ns average read latency, and under those assumptions the design-space exploration favors removing the shared LLC, reducing L1 latency through M3D layout, widening the pipeline, and exploiting dense vertical connectivity for synchronization. This does not directly establish the same conclusion for Mono3D DRAM, but it suggests that if Mono3D DRAM reaches comparable latency and bandwidth regimes, then architectural optimization above the memory stack may become at least as important as the memory organization itself (Ghiasi et al., 2022).

A common misconception is therefore to view Mono3D DRAM as a single technology with a single benefit. The literature instead presents a layered picture. In one line of work, it is a way to mitigate the long-standing DRAM latency–area tradeoff without abandoning 1T1C semantics. In another, it is a bandwidth-rich, latency-heterogeneous substrate for near-memory processing and application-specific placement. In a third, it is part of a broader family of monolithically integrated dynamic memories whose closest practical role may be LLC rather than main memory. What unifies these directions is not one fixed macro architecture, but the proposition that fine-grained vertical integration, if it can be routed, cooled, and manufactured, changes the optimization variables of memory design from the cell upward (Huang et al., 2020, Lu et al., 27 Feb 2026, Waqar et al., 8 Mar 2025).