MELISO+: Distributed RRAM In-Memory Computing

• MELISO+ is a full-stack, distributed framework for energy-efficient in-memory computing using RRAM crossbar arrays, featuring algorithm–hardware co-design and virtualization.
• It implements a two-tier error-correction mechanism that suppresses first- and second-order errors—reducing output error norms by over 90%—to enable high-accuracy matrix computations.
• The framework scales large matrix-vector operations up to 65,000×65,000 by partitioning tasks across MPI-enabled RRAM tiles for near-linear distributed execution.

Searching arXiv for MELISO+ and related RRAM in-memory computing papers. MELISO+ is a full-stack, distributed framework for energy-efficient in-memory computing with RRAM crossbar arrays, introduced as an extension of MELISO (“In-Memory Linear Solver”) for large-scale matrix-vector multiplication and linear solves under realistic device non-idealities (Vo et al., 18 Aug 2025). Its design couples algorithm–hardware co-design, a software-driven virtualization layer, and a two-tier error-correction mechanism intended to suppress device variability at runtime while enabling distributed execution of matrices up to $65{,}000\times65{,}000$ via MPI across $R\times C$ tiles of RRAM crossbars (Vo et al., 18 Aug 2025). In the broader lineage of RRAM benchmarking and solver design, MELISO+ is situated between the baseline device-aware VMM benchmarking framework MELISO (Chowdhury et al., 2024) and later optimization-oriented integrations in distributed in-memory primal-dual hybrid gradient methods (Vo et al., 25 Sep 2025).

1. Origins and conceptual scope

MELISO+ derives from MELISO, an end-to-end software framework built on top of the NeuroSim+ macro-model for device-aware benchmarking of analog vector–matrix multiplication in RRAM crossbar arrays (Chowdhury et al., 2024). MELISO exposes the relationship between device characteristics such as conductance window, precision, non-linear programming behavior, and cycle-to-cycle variability, and downstream computing accuracy metrics, thereby providing a basis for principled algorithm–device co-design (Chowdhury et al., 2024).

Within that trajectory, MELISO+ realizes several directions that MELISO had outlined only as prospective extensions: virtualization and parallelization primitives for arbitrarily sized crossbar arrays, integration with solver workflows, and advanced error-correction layers to trade off energy, latency, and accuracy (Chowdhury et al., 2024). In its defined form, MELISO+ comprises a Python front end called MelisoPy, a C++ engine built on NeuroSim+, first- and second-order error-correction modules implemented in C++ and Python, and a distributed backend using MPI (Vo et al., 18 Aug 2025).

Its primary objectives are threefold. First, it co-designs algorithms and hardware, specifically crossbar arrays with host CPU/GPU control, for large-scale matrix-vector multiplication and linear solves beyond the physical limits of a single RRAM tile (Vo et al., 18 Aug 2025). Second, it integrates a two-tier error-correction algorithm that suppresses device nonidealities at runtime, enabling low-precision RRAM devices to match or exceed the accuracy of “best-in-class” high-precision devices such as EpiRAM (Vo et al., 18 Aug 2025). Third, it supports distributed execution through partitioning, virtualization, and aggregation across multiple nodes (Vo et al., 18 Aug 2025).

A plausible implication is that MELISO+ should be understood less as a single kernel and more as a cross-layer computational stack: device model, array simulator, runtime correction, distributed orchestration, and application-facing solver interface.

2. System architecture and execution pipeline

At the interface level, MelisoPy specifies the problem size $\mathbf A\in\mathbb R^{m\times n}$, vector $\mathbf x\in\mathbb R^n$, device type, write-verify tolerance $\epsilon$, number of write-verify iterations $N$, and regularization $\lambda$ (Vo et al., 18 Aug 2025). The C++ engine, built on NeuroSim+, simulates analog MVM on each RRAM crossbar and returns noisy outputs together with energy and latency estimates (Vo et al., 18 Aug 2025). Error-correction modules then denoise the raw crossbar outputs, while the distributed backend partitions $\mathbf A$ and $\mathbf x$ across nodes and aggregates partial results via MPI (Vo et al., 18 Aug 2025).

The internal pipeline includes adjustableMatWriteAndVerify and adjustableVecWriteAndVerify, raw MVM evaluations for $A\tilde x$, $R\times C$0, and $R\times C$1, a first-order error-correction combiner, second-order denoising through denoiseLeastSquare, per-cell energy and latency accounting, distributed dispatch, and post-processing of relative error norms and scaling curves (Vo et al., 18 Aug 2025).

The relationship to the original MELISO pipeline is direct. MELISO already separated a forward pass, in which Python and Cython passed problem data and device parameters to a modified NeuroSim+ C++ backend, from a backward or analysis pass, in which hardware outputs were rescaled and compared against a software baseline $R\times C$2 (Chowdhury et al., 2024). MELISO+ retains that basic separation but adds runtime correction and distributed execution as first-class components (Vo et al., 18 Aug 2025).

In solver-oriented deployments, MELISO+ can also function as the physics-based analog MVM backend invoked by higher-level routines. In the distributed PDHG setting, matmulAccel calls MELISO+ to simulate each analog matrix–vector multiplication under realistic non-idealities, while host-side routines perform preprocessing, block-matrix construction, norm estimation, and iterative updates (Vo et al., 25 Sep 2025). In that formulation, MELISO+ supplies the energy, latency, and noisy MVM outputs on which the solver’s performance estimates depend (Vo et al., 25 Sep 2025).

3. Two-tier error-correction mechanism

The central algorithmic contribution of MELISO+ is a two-stage error-correction scheme that addresses first-order and second-order errors induced by RRAM programming variability (Vo et al., 18 Aug 2025). The framework models programmed quantities as

$R\times C$3

where $R\times C$4 is the device write-verify mapping and $R\times C$5 denotes per-element programming errors (Vo et al., 18 Aug 2025).

To cancel dominant first-order terms, MELISO+ forms three MVMs on the crossbar: $R\times C$6 It then combines them as

$R\times C$7

which yields

$R\times C$8

so that all $R\times C$9 terms vanish and only $\mathbf A\in\mathbb R^{m\times n}$0 terms remain (Vo et al., 18 Aug 2025).

The residual vector $\mathbf A\in\mathbb R^{m\times n}$1 is then processed by a second-order denoising stage based on Tikhonov-regularized least squares: $\mathbf A\in\mathbb R^{m\times n}$2 where $\mathbf A\in\mathbb R^{m\times n}$3 is the first-difference matrix with $\mathbf A\in\mathbb R^{m\times n}$4 on the diagonal and $\mathbf A\in\mathbb R^{m\times n}$5 on the superdiagonal (Vo et al., 18 Aug 2025). With $\mathbf A\in\mathbb R^{m\times n}$6, this step is reported to suppress residual second-order errors while preserving the smooth structure of $\mathbf A\in\mathbb R^{m\times n}$7 (Vo et al., 18 Aug 2025).

The quantitative effect reported for this two-tier scheme is substantial: first- and second-order error correction reduce $\mathbf A\in\mathbb R^{m\times n}$8 and $\mathbf A\in\mathbb R^{m\times n}$9 by more than $\mathbf x\in\mathbb R^n$0 on all device types compared to no error correction, in experiments averaged over 100 trials and two $\mathbf x\in\mathbb R^n$1 matrices with condition numbers $\mathbf x\in\mathbb R^n$2 and $\mathbf x\in\mathbb R^n$3 (Vo et al., 18 Aug 2025). This directly addresses a limitation documented in MELISO, where non-linearity and cycle-to-cycle variability could strongly inflate mean error and variance in VMM outputs (Chowdhury et al., 2024).

A common misconception is that RRAM accuracy must be obtained solely by moving to intrinsically high-precision devices. MELISO+ does not assume that premise. Instead, it explicitly reports that low-precision TaO$\mathbf x\in\mathbb R^n$4-HfO$\mathbf x\in\mathbb R^n$5 devices can achieve post-EC accuracy equal to EpiRAM while retaining major energy and latency advantages (Vo et al., 18 Aug 2025).

4. Distributed virtualization and scalability

MELISO+ addresses the physical size limits of a single crossbar tile through a virtualization and partitioning strategy for large matrices (Vo et al., 18 Aug 2025). In a multi-chiplet system of $\mathbf x\in\mathbb R^n$6 RRAM crossbars, each of size $\mathbf x\in\mathbb R^n$7, the native MVM capacity is $\mathbf x\in\mathbb R^n$8. To process matrices up to $\mathbf x\in\mathbb R^n$9, the framework applies zero-padding when $\epsilon$0 or $\epsilon$1, block partitioning into

$\epsilon$2

subblocks of size at most $\epsilon$3, and further subdivision into $\epsilon$4 subchunks aligned to the tile grid (Vo et al., 18 Aug 2025).

Each chunk $\epsilon$5 with matching $\epsilon$6 is sent to a distinct compute node through MPI, where local “write-verify + two-tier EC” MVM is performed and a partial $\epsilon$7 is returned; the final output $\epsilon$8 is assembled via MPI reduce (Vo et al., 18 Aug 2025). The framework reports near-linear weak scaling and strong scaling up to $\epsilon$9, with virtualization overhead diminishing as each crossbar approaches the native block size (Vo et al., 18 Aug 2025).

This virtualization strategy corresponds closely to the roadmap anticipated in MELISO, which had identified parallelization and virtualization for arbitrarily sized crossbar arrays as a future extension (Chowdhury et al., 2024). In MELISO+, it becomes operational infrastructure rather than a speculative direction.

In the PDHG-based distributed optimization setting, the same distributed logic is paired with a symmetric block-matrix representation $N$0, a one-time encode step, and repeated calls to matmulAccel without reprogramming the crossbar during the inner loop (Vo et al., 25 Sep 2025). This suggests that MELISO+ is not restricted to stand-alone MVM benchmarking; it can serve as a reusable substrate for iterative optimization algorithms whose dominant kernels are fixed linear operators.

5. Device, circuit, and performance model

MELISO+ is built around a physics-based RRAM crossbar model that includes device variability, parasitic circuits, peripheral overhead, and write-endurance considerations (Vo et al., 25 Sep 2025). In the PDHG deployment, each crossbar cell is represented by a conductance $N$1 controlled via write pulses, with read current

$N$2

where $N$3 for linear devices or $N$4 under nonlinearity (Vo et al., 25 Sep 2025). Device-to-device and cycle-to-cycle variability are modeled multiplicatively,

$N$5

and read noise is added as

$N$6

(Vo et al., 25 Sep 2025).

Array-level parasitics are incorporated through row and column wire resistance $N$7, with IR-drop handled by nodal analysis, while peripheral DAC and ADC energy and latency are also parameterized (Vo et al., 25 Sep 2025). The ideal analog MVM is

$N$8

and the non-ideal form includes variability, IR-drop, and noise (Vo et al., 25 Sep 2025). Energy and latency per MVM are modeled as

$N$9

(Vo et al., 25 Sep 2025).

The device-aware basis for this modeling is consistent with MELISO, which parameterized conductance window $\lambda$0, weight precision $\lambda$1, write non-linearity through an exponential update law, and cycle-to-cycle variability through a normal distribution on actual conductance after programming (Chowdhury et al., 2024). MELISO’s benchmarking demonstrated that increasing precision or memory window decreases MSE, while non-linearity and variability strongly worsen error distributions (Chowdhury et al., 2024). MELISO+ can therefore be seen as extending the same device-level realism into distributed execution and corrective runtime computation.

The following table summarizes architectural components explicitly identified for MELISO+.

Component	Role	Implementation context
MelisoPy	Problem specification and EC parameters	Python front end (Vo et al., 18 Aug 2025)
NeuroSim+-based engine	Analog MVM simulation, energy and latency reporting	C++ (Vo et al., 18 Aug 2025)
Error-correction modules	First- and second-order denoising	C++ and Python (Vo et al., 18 Aug 2025)
Distributed orchestrator	Partitioning, dispatch, reduction	MPI (Vo et al., 18 Aug 2025)

6. Quantitative characteristics and comparative position

MELISO+ reports performance in terms of write energy $\lambda$2, write latency $\lambda$3, and relative output error norms

$\lambda$4

where $\lambda$5 is ground truth and $\lambda$6 is the corrected output (Vo et al., 18 Aug 2025). Across the reported $\lambda$7 benchmarks, error correction reduces both $\lambda$8 and $\lambda$9 by more than $\mathbf A$0 on all device types (Vo et al., 18 Aug 2025).

For low-precision TaO$\mathbf A$1-HfO$\mathbf A$2 devices, the native write energy and latency are reported as $\mathbf A$3 and $\mathbf A$4, while EpiRAM is reported at $\mathbf A$5 and $\mathbf A$6 (Vo et al., 18 Aug 2025). After error correction, the low-precision devices achieve accuracy equal to EpiRAM while still offering $\mathbf A$7–$\mathbf A$8 orders of magnitude lower energy and $\mathbf A$9 lower latency (Vo et al., 18 Aug 2025). Compared to high-precision alternatives, MELISO+ reports end-to-end energy efficiency improvements of $\mathbf x$0–$\mathbf x$1 and latency reductions of $\mathbf x$2 (Vo et al., 18 Aug 2025).

The comparative argument is sharpened against alternative architectures. Conventional von Neumann designs with digital ECC are described as incurring $\mathbf x$3–$\mathbf x$4 latency overhead and large area and energy for parity bits, while single-tile RRAM MVM demonstrations are described as limited to $\mathbf x$5 scales and lacking onboard EC (Vo et al., 18 Aug 2025). High-precision devices such as EpiRAM are described as avoiding EC but at approximately $\mathbf x$6 higher energy per write and $\mathbf x$7 higher latency than TaO$\mathbf x$8-HfO$\mathbf x$9 combined with MELISO+ (Vo et al., 18 Aug 2025).

In the PDHG solver application, MELISO+ is associated with up to three orders of magnitude reductions in energy consumption and latency relative to GPU-accelerated solvers on large-scale linear programs (Vo et al., 25 Sep 2025). More specifically, the paper reports Step 1 energy reductions of $A\tilde x$0–$A\tilde x$1 with latency speedups up to $A\tilde x$2, Step 2 energy reductions up to approximately $A\tilde x$3 with latency speedups up to approximately $A\tilde x$4, and overall end-to-end savings ranging from $A\tilde x$5–$A\tilde x$6 for EpiRAM and $A\tilde x$7–$A\tilde x$8 for TaO$A\tilde x$9-HfO$R\times C$00, with corresponding latency speedups (Vo et al., 25 Sep 2025).

These results should not be conflated with claims about arbitrary application accuracy. The reported metrics are tied to specific workloads, device models, and benchmark settings. What they establish directly is that MELISO+ can alter the device-selection tradeoff by substituting runtime correction and distributed execution for brute-force hardware precision.

7. Applications, design implications, and research context

The most explicit application domain advanced for MELISO+ is high-dimensional AI computation. LLMs and generative AI are identified as depending heavily on large MVMs, including multi-head attention and fully connected layers, as well as iterative solvers such as mixture-of-experts routing (Vo et al., 18 Aug 2025). MELISO+ is described as mapping naturally to these workloads through tile-grid parallelism for very large matrices, low write energy and latency for inference and analog in-memory fine-tuning, two-tier error correction for per-layer numerical fidelity, and software virtualization for dynamic sparsity patterns and MoE sub-routing (Vo et al., 18 Aug 2025).

A second application context is large-scale linear optimization. In the PDHG formulation, MELISO+ models device physics, variability, noise, write endurance, IR drop, and ADC/DAC overhead while providing realistic analog MVMs for Lanczos norm estimation and PDHG iterations (Vo et al., 25 Sep 2025). A key co-design principle there is minimizing writes: the symmetric block mapping means $R\times C$01 and $R\times C$02 are never re-encoded, the crossbar is programmed once through closed-loop write-verify, and the inner loop changes only vectors rather than matrix conductances (Vo et al., 25 Sep 2025). Step sizes are then selected with a noise-aware safety margin so that convergence is guaranteed despite analog perturbations (Vo et al., 25 Sep 2025).

Several design implications follow directly from the combined MELISO and MELISO+ literature. First, device metrics such as memory window, precision, non-linearity, and variability remain first-order determinants of raw analog error (Chowdhury et al., 2024). Second, MELISO+ demonstrates that runtime algorithmic compensation can partially substitute for intrinsically higher device precision (Vo et al., 18 Aug 2025). Third, scalability in RRAM-based IMC depends not only on larger arrays but also on virtualization, partitioning, and host-level orchestration (Vo et al., 18 Aug 2025). Fourth, optimization and AI workloads benefit when algorithms are reformulated to reduce reprogramming frequency, since write cycles carry both energy cost and endurance implications (Vo et al., 25 Sep 2025).

The principal controversy addressed by this body of work concerns whether analog RRAM non-idealities fundamentally preclude accurate large-scale computation. MELISO documented the severity of those non-idealities in benchmark VMM settings (Chowdhury et al., 2024). MELISO+ responds not by denying the underlying device constraints, but by embedding correction, virtualization, and solver-aware scheduling into the execution stack (Vo et al., 18 Aug 2025). This suggests a research program in which device physics, architecture, and numerical algorithms are treated as inseparable layers of the same computational system.