LMM-IR: Netlist-Aware IR-drop Prediction
- LMM-IR is a multimodal framework that integrates netlist topology as 3D point clouds with 2D circuit property maps to predict static IR-drop.
- It employs a dual-stream architecture with transformer-based netlist encoding and convolutional circuit feature extraction, achieving high F1 and low MAE.
- The approach reduces analysis turnaround time, making it suitable for iterative design workflows in large-scale chip design optimization.
LMM-IR is a netlist-aware multimodal deep-learning framework for static IR-drop prediction in large-scale chip designs. The approach integrates transformer-based representations of netlist topology, processed as 3D point clouds, with conventional 2D circuit property maps. This architecture enables efficient, accurate prediction of per-pixel voltage drop (static IR-drop) across entire power distribution networks (PDNs) for circuits with hundreds of thousands to millions of nodes, substantially reducing analysis turnaround time while matching or exceeding prior state-of-the-art predictive performance (Ma et al., 16 Nov 2025).
1. Architecture and Data Modalities
LMM-IR consists of four major components: a Circuit Encoder, a Large-scale Netlist Transformer (LNT), a Multimodal Fusion Module, and a Decoder for IR-drop prediction. The input pipeline processes both the SPICE netlist (representing circuit connectivity and device attributes) and 2D circuit property maps, such as current demand, PDN density, effective distance, voltage-source plots, and resistor-density. The netlist is transformed into a sparse 3D point cloud reflecting inter-node electrical/physical properties. All input modalities are embedded into a high-dimensional latent space for integration via cross-modal attention before spatial upsampling yields the predicted voltage drop map.
The architectural data flow is summarized by the following block diagram (ASCII form from the original source):
5 This schema reflects the dual-stream embedding of spatial (image-like) and topological (point-cloud) data, followed by joint representation learning and upsampling.
2. Netlist Representation via Large-scale Transformers
The key innovation is encoding netlist topology as a large-scale point cloud suitable for self-attention-based neural architectures. Each netlist element is represented as an 8-dimensional point: with spatial coordinates of node terminals, the element value (resistance, current, or voltage), a one-hot-encoded device type, and the metal layer indices. The full point cloud is embedded to dimension by a trainable linear or MLP layer.
Stacked point embeddings (for elements) feed into an -layer transformer with standard scaled dot-product self-attention and residual feed-forward blocks:
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This approach scales to 3–4 points by exploiting the sparsity inherent in netlists, maintaining manageable memory scaling 5.
3. Multimodal Fusion and Joint Embedding
The circuit property maps are processed by a downsampling convolutional encoder (with four strided blocks, U-Net style), yielding a feature tensor 6. This is flattened to a sequence of 7 tokens of dimension 8. Each layout is padded or rescaled to 9 spatial resolution.
Multimodal fusion is achieved by mutual cross-attention between the netlist and circuit feature tokens. For example, circuit tokens 0 query netlist tokens 1 in cross-attention layers: 2
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This bidirectional attention captures complex relationships between spatial circuit attributes and topological connectivity. The final representation concatenates or merges these token sequences before decoding.
4. Static IR-Drop Prediction and Loss
The decoder reconstructs a 4 pixel per-point IR-drop map through four upsampling (deconvolution) layers and a final 5 convolution. The training loss is mean square error (MSE) between predicted 6 and true voltage-drop maps 7: 8 No cross-entropy or F1-based losses are used during training; F1 is strictly an evaluation metric.
5. Training Procedures and Dataset Specification
Training employs the ICCAD 2023 dataset, comprising 100 synthetic and 10 real layouts, with 10 hidden real test circuits (sizes ranging from 9 to 0 netlist nodes). Data augmentation is applied by oversampling synthetic (×10) and real (×20) layouts, and importing 2,000 additional layouts, for a total of 3,310 training samples.
Key training parameters are:
- Input tile size: 1
- Batch size: 2
- Optimizer: Adam, initial learning rate 3
- 200 total epochs
- Channel-wise normalization to zero mean, unit variance
Each circuit is processed in two modalities: (1) spatial circuit property maps, and (2) 3D netlist point cloud. The pseudocode in the original source outlines preprocessing, forward pass, fusion, decoding, and backpropagation (Ma et al., 16 Nov 2025).
6. Empirical Performance and Comparative Evaluation
LMM-IR is evaluated on concealed real-world circuits from ICCAD 2023, using three primary metrics:
- F1 score for top 10% IR-drop (“hot nodes”)
- Mean Absolute Error (MAE) in volts:
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- Turn-Around Time (TAT) in inference seconds per GPU
Performance on the hidden test circuits (average across 10 cases):
| Model | F1 | MAE (×10⁻⁴ V) | TAT (s) |
|---|---|---|---|
| 1st Place | 0.46 | 1.35 | 14.8 |
| 2nd Place | 0.45 | 1.50 | 3.04 |
| IREDGe | 0.13 | 6.28 | 2.02 |
| IRPnet | 0.03 | 3.98 | 2.54 |
| LMM-IR | 0.58 | 1.35 | 3.05 |
LMM-IR achieves the highest F1 and the lowest MAE on average, with competitive inference speed (TAT). It wins 6/10 test cases by F1 (Ma et al., 16 Nov 2025).
7. Significance and Implications
LMM-IR demonstrates that direct multimodal integration of explicit netlist topology and spatial property maps enables scalable and accurate IR-drop prediction in modern chip design contexts. Its transformer-based netlist point-cloud module efficiently manages extremely large netlists while preserving crucial circuit-theoretic relationships, in contrast to prior image- or grid-based solutions. The result is not only improved MAE and hot-node F1 but also a substantial reduction in required analysis time, suggesting applicability for iterative design closure workflows or real-time design feedback. A plausible implication is that similar multimodal point-cloud+image transformer methods could be adapted for other EDA analysis tasks involving large, non-Euclidean circuit structures.
For full architecture specification, formulas, and reproducibility guides, see (Ma et al., 16 Nov 2025).