Hybrid CXL-over-XLink Design

• Hybrid CXL-over-XLink design is a hierarchical interconnect architecture that uses on-cluster XLink for low-latency accelerator communication and CXL for coherent inter-cluster memory pooling.
• It addresses critical challenges in data movement and synchronization in AI training, distributed OLTP, and model inference by clearly partitioning local versus remote traffic.
• Quantitative studies highlight performance gains—up to 7.3× throughput improvement and significant latency reductions—demonstrating its practical benefit in scale-up systems.

Hybrid CXL-over-XLink Design denotes a class of hierarchical interconnect and memory architectures in which accelerator-native links collectively termed XLink remain the local communication substrate, while Compute Express Link (CXL) provides the coherent inter-cluster and memory-pooling layer. In the literature, the term usually does not denote a literal tunneling scheme. The most faithful characterization is “a hierarchical heterogeneous hybrid fabric with interface abstraction through CXL,” in which XLink is retained inside accelerator clusters and CXL is used over, around, and across those clusters for shared memory, composable disaggregation, and heterogeneous federation (Woo et al., 16 Oct 2025, Jung, 9 Jul 2025).

1. Conceptual basis and architectural motivation

The hybrid design emerges from a common diagnosis across recent work: modern AI and data systems are constrained less by arithmetic throughput than by data movement, synchronization, and memory capacity. In LLM training and inference, recommendation, KV-cache-heavy serving, and retrieval-augmented generation, the dominant costs are inter-device communication, shared-state movement, and memory oversubscription rather than isolated compute throughput (Jung, 9 Jul 2025). In distributed OLTP, the same problem appears in another form: once data exceeds one machine’s DRAM, network-based transaction processing pays PCIe/NIC data movement, asynchronous NIC signaling, protocol-stack processing, and the absence of hardware cache coherence, with DrTM-H losing more than 53.3% throughput as remote access ratio rises from 0% to 100% (Wang et al., 16 Feb 2025).

Within this setting, XLink and CXL solve different problems. XLink is optimized for direct accelerator transfers, high bandwidth, low latency, and tightly coupled collective communication inside a local cluster. CXL supplies memory pooling, switch cascading, routing flexibility, multi-host sharing, and protocol-level coherence. The hybrid design exists because neither interconnect is sufficient by itself: XLink alone is insufficient because it lacks scalable multi-level fabric support, coherent memory sharing across large domains, and interoperability across distinct link ecosystems, while CXL alone is insufficient because it is “suboptimal for latency-sensitive accelerator communication at large scale” (Woo et al., 16 Oct 2025).

A recurrent misconception is to equate hybrid CXL-over-XLink with uniform end-to-end coherent tunneling. The literature instead describes a role-partitioned hierarchy: XLink serves the hot local data path, and CXL serves coherent scale-up, composable memory, and inter-cluster composition (Jung, 9 Jul 2025).

2. Hierarchical organization and traffic partitioning

The canonical organization is hierarchical. Inside a cluster, accelerators communicate over XLink; across clusters, those XLink-based clusters are connected through a CXL fabric built from hierarchical, multi-level switches with switch cascading and port-based routing. Parallel to the accelerator clusters are dedicated memory nodes attached to the same CXL hierarchy (Woo et al., 16 Oct 2025).

Concrete instantiations in the literature are explicit. ScalePool describes NVLink clusters with NVSwitches supporting up to 72 GPUs per rack, and UALink clusters that are theoretically scalable to 1,024 accelerators in a single-hop topology, though practical rack-scale deployments are described as being around 72 accelerators per rack (Woo et al., 16 Oct 2025). The broader hybrid report groups NVLink / NVLink Fusion and UALink under the umbrella term XLink, and places them inside rack-scale or cluster-scale accelerator groups, with CXL switch trays or middle-of-rack units extending the coherent scale-up domain beyond a single node or rack (Jung, 9 Jul 2025).

The traffic split is explicit rather than emergent.

Layer	Primary link	Typical role
Intra-cluster accelerator domain	XLink	tensor exchange, gradient synchronization, bulk local movement
Inter-cluster sharing domain	CXL	coherent memory sharing, inter-cluster communication, memory pooling
Longer-distance scale-out	Ethernet / InfiniBand / RDMA	non-local communication beyond the local scale-up boundary

Within this hierarchy, CXL subprotocol specialization matters. CXL.cache is used for coherent access and protocol-level cache coherence, CXL.mem for memory access semantics, and CXL.io for device management and, in some proposals, bulk or control-oriented transactions (Jung, 9 Jul 2025). This specialization is not uniform across all tiers. ScalePool explicitly proposes “coherence-centric CXL” for tier-1 and “capacity-oriented CXL” for tier-2, with selective deactivation of some CXL functions where full coherence is unnecessary (Woo et al., 16 Oct 2025).

The same boundary logic appears in other domains. DFabric, although framed as CXL-Ethernet, argues that local high-bandwidth fabrics should be extended only as far as their economics, topology, and signaling allow, after which traffic should cross an explicit boundary through pooled gateway resources rather than naïve per-host uplinks (Zhang et al., 2024). This suggests that a Hybrid CXL-over-XLink design is best understood as a bounded coherent scale-up fabric rather than an attempt to stretch one local link technology across every distance regime.

3. Coherence architecture and memory semantics

The coherence model is the central differentiator between a hybrid design and a simple multi-link cluster. Within a pure XLink domain, the literature describes unified addressability without protocol-level coherence. UALink organizes memory as a NUMA-like domain, and NVLink uses virtualization techniques for unification, but sharing beyond static partitions still requires explicit software-managed copying (Woo et al., 16 Oct 2025). CXL extends this by allowing selected memory regions to be exposed as cache-coherent regions across cluster boundaries, and in stronger designs by embedding dedicated CXL coherence logic alongside the XLink controller inside accelerators (Woo et al., 16 Oct 2025).

A second misconception is that the optimal hybrid design should preserve full native CXL coherence across every shared region. The strongest counterexample is CtXnL, which argues that vanilla CXL memory sharing is too expensive for transaction processing because standard coherence incurs high remote cache signaling cost and centralized snoop-filter overhead. In the prototype, core-to-core remote-cache signaling was about 847 ns versus 456 ns core-to-memory; in the idealized ASIC estimate it was 246 ns versus 170 ns. The same work estimates that worst-case centralized snoop-filter tracking for a 16-node system would require 1.8 billion entries, about 14.4 GB of directory memory (Wang et al., 16 Feb 2025).

CtXnL therefore splits the memory substrate into two coherence paths. Metadata fields such as locks, timestamps, indexes, latches, tuple headers, and other control state remain on vanilla CXL primitives with strict coherence, while record/value fields use a loosely coherent path with four operations: Local-Load (L-Ld), Local-Store (L-St), Global Synchronization (GSync), and Withdraw (Wd). The key lesson is “coherence only at transaction boundaries”: software concurrency control preserves correctness, while explicit publication and withdrawal avoid paying full coherence cost on every access (Wang et al., 16 Feb 2025). For Hybrid CXL-over-XLink, this suggests that a higher-latency transport should not inherit full end-to-end coherence indiscriminately; it should narrow the strict-coherence domain to metadata, synchronization state, and explicitly published data.

More general CXL memory-sharing work reaches a similar conclusion. For CXL 3.0, one proposed hybrid mechanism uses a small critical region of shared HDM tracked precisely in hardware for atomics, semaphores, queue-pairs, and metadata, while the rest of the large shared region is managed with software coherence or consistency (Jain et al., 2024). At the programming-model level, CXL0 formalizes remote memory with Load, LStore, RStore, MStore, LFlush, and RFlush, and explicitly states that CXL guarantees span accesses to a single cacheline and do not guarantee ordering between accesses to different memory locations (Assa et al., 2024). This reinforces the view that hybrid interconnect design must preserve the observable completion and visibility semantics of selected memory operations, not merely transport bytes.

4. Tiered memory and disaggregated capacity

Hybrid CXL-over-XLink systems are simultaneously interconnect designs and memory-hierarchy designs. The dominant pattern is a two-tier or multi-tier structure. In ScalePool, Tier-1 is the latency-critical layer: accelerator-local high-speed memory, such as on-package HBM or accelerator-attached DDR, combined with XLink and coherence-centric CXL. Tier-2 consists of dedicated memory nodes physically separated from accelerators and connected by a dedicated CXL fabric, intended for embedding tables, large caches, external knowledge bases, and capacity overflow (Woo et al., 16 Oct 2025).

The broader hybrid report adopts the same logic. It places hot data in accelerator-local HBM or local high-bandwidth memory, aggregates local memory across accelerators with XLink, and then uses CXL-attached pooled memory as a larger, somewhat slower tier. It describes CXL latency as roughly 100–250 ns, in contrast to RDMA or network-latency overhead often > 1 µs, and describes tier-2 CXL memory pool accesses as being in the tens to hundreds of ns range (Jung, 9 Jul 2025). This suggests that hybrid CXL-over-XLink is best treated as a deliberate locality hierarchy rather than a flat memory fabric.

The endpoint side of this hierarchy can itself be heterogeneous. CXL-GPU integrates multiple CXL root ports directly into the GPU so that different address ranges can map to DRAM-based or SSD-based CXL endpoints. To hide backend media variation, it introduces speculative read and deterministic store, and reports a siliconized controller with two-digit nanosecond roundtrip latency (Gouk et al., 18 Jun 2025). ITME extends the same pattern to disaggregated inference-state expansion: T1 GPU memory, T2 host DRAM, and T3.5 remote disaggregated CXL-hybrid memory, with an internal SSD-backed tier inside the remote appliance. It exploits the deterministic access patterns of model weights and prefix caches to prefetch data across the memory-storage hierarchy and reports up to a 35.7% throughput improvement over conventional CPU-offloading (Jang et al., 10 Jun 2026).

These examples show that “hybrid” refers not only to combining XLink and CXL, but also to combining coherence-centric near memory with capacity-oriented remote memory, sometimes backed by DRAM, sometimes by SSD, and sometimes by both.

5. Bridging, control planes, and research infrastructure

Because hybrid CXL-over-XLink designs straddle multiple communication regimes, the bridge or gateway layer becomes a first-class architectural component. DFabric makes this explicit. At the fabric boundary, a gateway complex must perform protocol conversion, address mapping / translation, routing domain separation, consistency boundary management, isolation boundary enforcement, and reordering and sequencing logic when traffic moves between local memory-semantic domains and wider networked domains (Zhang et al., 2024). The hybrid CXL-over-XLink report identifies the same issue and proposes specialized SoC bridging interfaces, streamlined interconnect protocols, and optional HBM integrated into bridge interfaces to cache frequently used requests or pre-converted formats (Jung, 9 Jul 2025).

The control plane in these systems is therefore distinct from the data plane. Configuration, mapping, and orchestration occur through host firmware, bridge logic, or runtime software; high-rate data motion follows XLink for local accelerator traffic and CXL or CXL-like memory semantics for shared regions. This separation also appears in transaction-oriented systems: CtXnL moves synchronization into explicit queue-based control paths, while leaving ordinary loads and stores on the memory path (Wang et al., 16 Feb 2025).

Simulation work reflects the same decomposition. ESF models CXL systems with an interconnect layer for arbitrary topology construction and routing, and a device layer for requesters, memory devices, switches, buses, and device-handled coherence via a DCOH realized as an inclusive snoop filter. It supports chain, tree, ring, spine-leaf, and fully-connected topologies, explicit PBR-style switch behavior, and duplex link studies, making it directly relevant to evaluating how CXL transaction semantics might be preserved over a different transport substrate (An et al., 2024). This suggests that the most practical path to hybrid design is to preserve CXL-oriented endpoint and coherence semantics while substituting or augmenting the underlying link model.

6. Quantitative behavior, constraints, and open questions

The performance literature supports the hybrid approach, but only under strict architectural conditions. ScalePool reports 1.22× on average and up to 1.84× LLM training speedup relative to a conventional RDMA-based baseline, with 3.79× average inter-cluster communication speedup, and a tier-2 disaggregated-memory latency reduction of up to 4.5× for memory-intensive workloads (Woo et al., 16 Oct 2025). The broader CXL-centric report attributes large end-to-end gains in RAG, DLRM, and MPI/HPC cases to coherent memory sharing and reduction of RDMA/software-mediated data movement, and uses those results to motivate a hybrid CXL/XLink hierarchy rather than uniform dependence on either interconnect alone (Jung, 9 Jul 2025).

The transactional literature is even sharper about latency sensitivity. CtXnL reports up to 2.08× greater throughput than vanilla CXL memory sharing, 6.47× over traditional network-based architectures, and as much as 7.3× over a CXL-RPC shared-nothing design on poorly partitioned workloads. It reduces average remote signaling cost by 65.9% on the prototype, reduces over 95% of cross-node coherence traffic overall, and shows that its throughput advantage can rise to 3.41× when link latency approaches 1 µs (Wang et al., 16 Feb 2025). This is highly specific evidence that if XLink layering increases effective coherence roundtrip cost, selective coherence becomes more valuable, not less.

At the same time, the literature identifies real pathologies. CXL-enabled tiered memory can degrade local DDR performance because slow remote requests occupy shared host-side queues; the disparity in memory-tier parallelism can reduce DDR bandwidth by up to 81% under heavy loads (Yang et al., 22 Mar 2025). This suggests that a Hybrid CXL-over-XLink design must include tier-aware admission control, protected local-memory service, and careful queue partitioning rather than assuming remote memory is “just slower DRAM.”

Several open issues remain unresolved. Protocol conversion and physical/logical transformation overheads are explicitly acknowledged in hybrid CXL/XLink proposals (Jung, 9 Jul 2025). Scaling beyond a rack is repeatedly described as problematic because of latency, failure-domain enlargement, broadcast-style synchronization, and I/O-port limits (Wang et al., 16 Feb 2025). Formal memory-model treatment also remains incomplete: some work defines only partial-order visibility narratives or operation-level abstractions rather than a standardized end-to-end hybrid consistency model (Assa et al., 2024). A plausible implication is that future Hybrid CXL-over-XLink systems will continue to narrow strict coherence to selected regions, rely on explicit publication and prefetch for most capacity tiers, and treat the bridge as a semantic transformer rather than a transparent packet tunnel.