Guarded Aggressive Undervolting (GAV)

Updated 5 December 2025

Guarded Aggressive Undervolting (GAV) is a technique that safely reduces operating voltage below standard guardbands using integrated error management to achieve high energy efficiency.
It leverages hardware, firmware, and software guards to detect and correct timing errors and data corruption in systems like CPUs, FPGAs, and DNN accelerators.
GAV dynamically balances energy savings, performance, and reliability through closed-loop control and fine-grained voltage adjustments based on real-time error monitoring.

Guarded Aggressive underVolting (GAV) is a methodology and associated set of hardware and algorithmic techniques designed to exploit the significant voltage guardbands present in digital systems—such as DNN accelerators, CPUs, FPGAs, and memory subsystems—for maximal energy efficiency. GAV achieves this by selectively pushing the supply voltage below traditional guardband limits, using architectural or algorithmic “guards” to detect, correct, or mask errors caused by timing violations and data corruption, and dynamically balancing the trade-offs among energy, performance, and reliability. In contrast to naive undervolting approaches, which either maintain wide guardbands or accept uncontrolled reliability loss, GAV leverages hardware-, firmware-, or software-level guards and closed-loop control strategies to maintain system correctness and resilience (Zhang et al., 2018, Fornt et al., 28 Nov 2025, Larimi et al., 2020, Papadimitriou et al., 2021, Nascimento et al., 2022, Mitard et al., 15 Apr 2025, Rinkinen et al., 17 Oct 2024, Salami et al., 2020, Salami et al., 2020, Göttel et al., 2021).

1. Fundamental Principles and Voltage Margins

Conventional digital systems maintain large voltage guardbands to absorb worst-case process, voltage, temperature, and aging-induced variations. The supply voltage ( $V_\mathrm{nominal}$ ) thus exceeds the minimum needed for correct operation under typical conditions ( $V_\mathrm{min}$ ), leading to quadratic energy inefficiency,

$P_\mathrm{dyn} = \alpha C V^2 f$

where $\alpha$ is switching activity, $C$ is load capacitance, and $f$ is clock frequency. For instance, HBM devices exhibit a 19% guardband (1.20 V $\to$ 0.98 V) that, when eliminated, yields a 1.5× power reduction without faults, while further voltage reduction can achieve 2.3× savings but at the cost of error rates that must be actively managed (Larimi et al., 2020).

In modern FPGAs, guardbands of up to 400 mV permit operation (e.g., 850 mV $\to$ 570 mV on ZCU102) at full frequency and accuracy; additional undervolting enters a “critical region” with rapid timing fault onset and device-level instability below $V_\mathrm{crash}$ (Salami et al., 2020).

GAV codifies the “guarded” region as that which affords zero or tolerable errors—possibly augmented by error correction, redundancy, or application-level resilience—and introduces the possibility of “aggressive” operation below this margin, contingent on runtime error monitoring and recovery (Fornt et al., 28 Nov 2025, Nascimento et al., 2022, Rinkinen et al., 17 Oct 2024).

2. GAV Mechanisms: Error Detection, Recovery, and Control Loops

GAV employs tightly integrated detection/recovery mechanisms to enable safe undervolting. For custom accelerators, hardware-level guards such as Razor flip-flops detect bit-level timing errors by sampling data on both master and delayed shadow latches; detected mismatches trigger pipeline replay or fine-grained recovery, maintaining correctness at undervolted conditions while bounding performance penalties (e.g., CPI increase ≈1-2%) (Zhang et al., 2018). In embedded multicore MPSoCs, redundancy (DMR, TMR) and safe core coordination enable error detection, rollback, and replay below datasheet guardbands (Nascimento et al., 2022).

Software-centric GAV systems (e.g., Shavette) instrument computation with Algorithm-Based Fault Tolerance (ABFT) and Double-Modular Redundancy (DMR) at the algorithmic layer: matrix checksum validation or duplicated implementation comparisons are used to trigger rollback (by raising voltage and rerunning inference) upon error detection, exploiting the large margin provided by error-free execution at reduced voltage and resorting to recovery only as needed (Rinkinen et al., 17 Oct 2024).

Closed-loop dynamic voltage controllers adjust $V$ in fine steps (e.g., 5-10 mV), probing for first-failure conditions or continuous error rates, and rolling back to the last known good voltage as soon as the error metric exceeds a pre-set threshold. For systems with workload and environmental variability, these loops can track per-frequency, per-core, or per-layer guardbands and adapt on device aging or thermal drift (Papadimitriou et al., 2021, Göttel et al., 2021).

3. Implementation Paradigms Across Domains

DNN Accelerators and Specialized Hardware

Systolic and bit-serial DNN accelerators: GAV can be realized with per-MAC or per-slice undervolting and fine-grained error detection. For example, GAVINA applies supply voltage overscaling only to selected LSB slices in bit-serial MACs, controlling aggressiveness via a threshold parameter $G$ that specifies the number of undervolted slices. By configuring protected and approximate voltage islands within the compute fabric, the architecture balances the power savings from undervolting against the significance and correctability of bit errors, preserving application-level accuracy (e.g., $\leq 0.1\%$ degradation for $20\%$ + energy gains on ResNet-18/CIFAR-10) (Fornt et al., 28 Nov 2025).
Hybrid software/hardware approaches: Algorithmic error detection is applicable to commodity accelerators, with ABFT and DMR implemented in DNN inference pipelines, supporting energy savings of 18-25% with <4% throughput loss, and zero circuit modification (Rinkinen et al., 17 Oct 2024).

CPUS, MPSoCs, DRAM, and FPGA Subsystems

CPUs and MPSoCs: Automated frameworks characterize per-core per-frequency $V_\mathrm{min}$ by voltage sweep and error logging (SDC, CE, UE, hang). GAV selects an “aggressive” $V_\mathrm{agg}$ just above $V_\mathrm{min}$ plus a tunable guard, deploying them via OS or firmware DVFS drivers and monitoring error counters for reliability assurance (Papadimitriou et al., 2021, Nascimento et al., 2022, Göttel et al., 2021).
HBM and memory arrays: Fine-grained GAV policies select the minimum $V$ such that per-channel fault rates and required memory capacity are satisfied for a given application, leveraging a runtime-maintained “FaultMap” to exclude or remap error-prone pseudo-channels as voltage is reduced, trading off memory capacity for additional energy savings as permissible (Larimi et al., 2020).
FPGA subsystems: Both on-chip BRAMs and FPGA logic can be run below guardband. For BRAMs, device- and tile-level vulnerability maps and built-in ECC (SECDED) are combined in GAV to enable operation at $>90\%$ energy savings with negligible accuracy loss ( $<0.1\%$ ) given application-level fault masking, physical BRAM mapping, and ECC correction (Salami et al., 2020). For logic, the interplay of supply, critical path delay, and workload temperature is characterized to maximize the energy-efficiency margin, with clock-frequency compensation optionally available to further extend reliability (Salami et al., 2020).

4. Quantitative Trade-offs: Energy, Performance, Reliability

Global energy reduction is driven by the quadratic voltage law. Across domains, GAV consistently demonstrates superlinear energy efficiency improvement by eliminating conservative guardbands and then carefully managing the first-fault region:

Application	Guardband Range	Energy Savings (GAV)	Error Rate Bound	Throughput Penalty	Reference
DNN Accel	$\sim$ 20-100mV	35-60% ( $\leq1\%$ acc loss)	$<1\%$ timing errors	$<2\%$ CPI	(Zhang et al., 2018)
GAVINA	multi-tier	20-95% (sys-level)	$<0.1\%$ output acc loss	none (bit-serial)	(Fornt et al., 28 Nov 2025)
HBM	1.2 $\to$ 0.98V	1.5 $\times$ (no faults); 2.3 $\times$ (with faults)	application-defined	none	(Larimi et al., 2020)
MPSoC	1.2 $\to$ 1.0V	up to 27%	runtime error rollback	$<2\%$ overhead	(Nascimento et al., 2022)
FPGA CNN	850 $\to$ 570mV	2.6 $\times$	zero accuracy loss	none	(Salami et al., 2020)

Empirically, guardband elimination alone yields significant savings (e.g., 2.6 $\times$ in FPGAs with zero accuracy loss), while deeper undervolting further increases savings at the price of rising (though managed) fault rates. Frequency underscaling can be applied for additional robustness but reduces throughput (Salami et al., 2020).

5. Modeling, Characterization, and Calibration

GAV requires accurate characterization of the voltage-fault-performance space. Experimental platforms perform voltage-frequency sweeps with built-in workloads and error checkers. The error rate increases exponentially or logistically as $V$ drops below $V_\mathrm{min}$ :

$P_\mathrm{error}(V) \approx \alpha \cdot \exp(\beta \cdot (V_\mathrm{nominal} - V))$

Calibration involves identifying $V_\mathrm{guard} = V_\mathrm{hib} + \Delta V_\mathrm{safety}$ where $V_\mathrm{hib}$ is the brownout (hibernation) threshold for functional logic, with margins determined by sensor latency, process, and thermal variation (Mitard et al., 15 Apr 2025).

Sophisticated error models (e.g., in bit-serial accelerators) can apply empirical LUTs indexed by bit position, previous cycle states, and word population to sample per-cycle fault probabilities at undervolted LSB slices (Fornt et al., 28 Nov 2025).

Runtime GAV controllers dynamically probe for the point of first error, track error rates in a sliding window, and enforce recovery or raising of voltage when error rates exceed thresholds (e.g., $<10^{-12}$ faults/instruction for ARM SoCs (Göttel et al., 2021)).

6. Security Considerations and Side-Channel Countermeasures

Voltage underscaling can have security implications. “Chypnosis”-style attacks leverage rapid undervolting to induce brownout or hibernation and extract data via static side-channels while bypassing voltage and clock tamper sensors. GAV, when deployed in security-sensitive settings, must maintain $V_\mathrm{guard}$ and $t_\mathrm{guard}$ above empirically validated thresholds so that all guard/SCA-evasion logic remains functional:

Guarding against attacks entails faster comparators, multi-threshold sensing, and always-on asynchronous circuit-level self-destruct for key storage.
Recommended margins: $V_\mathrm{guard} = V_\mathrm{hib} + \Delta V_\mathrm{safety}$ (typically 50–100 mV above hibernation), $t_\mathrm{guard} \leq t_\mathrm{sense} - \Delta t_\mathrm{margin}$ (Mitard et al., 15 Apr 2025).

These countermeasures can reduce energy savings by requiring less aggressive undervolting or additional circuitry, but are essential for robust SCA resistance.

7. Comparative Analysis and Future Trends

GAV generalizes and outperforms traditional undervolting and TED (Timing Error Detection) approaches by integrating software, architectural, and hardware-level error management, and by enabling per-region, per-layer, or per-slice voltage control. In DNN accelerators, GAV-based bit-serial mixed-precision implementations (e.g., GAVINA) match or exceed state-of-the-art in energy efficiency, offering fine-grained trading between energy, accuracy, and performance not available with static TED-only schemes (Fornt et al., 28 Nov 2025).

A plausible implication is that widespread deployment of GAV-style control in scalable cloud/server and edge environments can substantially improve overall compute efficiency without architectural redesign—provided the necessary runtime, monitoring, and error-correction primitives are integrated into OS and firmware stacks.