Griffin Architecture: Digital DAQ Infrastructure

• Griffin architecture is a high-performance digital DAQ system designed for advanced nuclear decay-spectroscopy experiments, offering rigorous event tracking and low dead-time performance.
• It employs a three-tier, firmware-embedded pipeline with front-end digitizers, data concentrators, and a master module to achieve high throughput and precise timing.
• The system supports simultaneous multi-detector operation with advanced signal processing, ensuring sub-0.05% measurement uncertainty in high-rate experiments.

The Griffin architecture is a term used for a set of high-performance digital systems and data acquisition infrastructure developed for the GRIFFIN (Gamma-Ray Infrastructure For Fundamental Investigations of Nuclei) spectrometer at TRIUMF-ISAC. It underpins high-rate, low-dead-time decay-spectroscopy experiments and is characterized by a three-tier digital data acquisition (DAQ) pipeline with firmware-embedded signal-processing, event filtering, and rigorous event traceability. The architecture enables precise half-life and branching-ratio measurements with total dead-time and accounting uncertainty well below 0.05%, at high channel rates and with scalable multi-detector operation (Garnsworthy et al., 2017).

1. Hardware Architecture

Griffin's DAQ is physically distributed across three major tiers, each specialized for the acquisition, aggregation, control, and time synchronization of detector signals. All modules employ 6U VME64x cards for standard backplane power, control, and I/O.

• Tier 1: Front-End Digitizers
  • GRIF-16: 16 channels, 14-bit, 100 MS/s, Arria-V FPGA + FMC slot.
  • GRIF-4G: 4 channels, 12-bit, 1 GS/s, Stratix+Cyclone IV FPGAs.
  • Inputs: HPGe preamps (SMA/MCX), PMTs from scintillators, Si(Li) preamps.
  • Outputs: Gigabit mini-SAS (to GRIF-C), SFP Ethernet (control), eSATA clock/sync. On-board Nios II CPU with μC/OS-II and MIDAS server implementations.
• Tier 2: Data Concentrators
  • GRIF-C Slave: Stratix IV GX + 3× Spartan 6 on FMCs. Up to 16× mini-SAS inputs, upstream mini-SAS to Master, local DRAM/micro-SD for buffering.
• Tier 3: Master & System Control
  • GRIF-C Master: Identical hardware as Slave, but with Master-mode firmware. Applies global event filtering and dispatches accepted events to MIDAS frontend over SFP (1 GbE, planned 10 GbE).
  • GRIF-Clk Master/Slaves: Houses a chip-scale atomic clock (CSAC, 10 MHz → 50 MHz), fans out clock/sync over eSATA with measured <700 ps skew and <16 ps jitter.
  • GRIF-PPG: Cyclone III FPGA, for programmable pattern and sequence output (32 LEMO TTL/NIM + 4 inputs) to coordinate external actuators (tape/beam) via VME.

Data path: Detectors → Preamplifier → GRIF-16/4G → mini-SAS (5 Gb/s) → GRIF-C Slave → mini-SAS → GRIF-C Master → SFP → MIDAS → Disk. All elements are globally synchronized to the CSAC-derived clock.

2. Digital Signal Processing Pipeline

The signal processing chain is implemented tightly in firmware on the digitizer FPGAs, performing real-time hit discrimination, energy extraction, timing, and pile-up/summing logic.

Pipeline Stages

• Hit Detection Three FIR filters (difference, decay-correct, integrate) are executed for each sample:

  $A_n = v_n - v_{n-T^{\mathrm{dif}}}$

  $$B_n = \frac{1}{T^{\mathrm{dec}}}\sum_{i=1}^{T^{\mathrm{dif}}}A_{n-i}$$

  $$C_n = \frac{1}{T^{\mathrm{int}}}\sum_{i=0}^{T^{\mathrm{int}}-1}(A_{n-i} + B_{n-i})$$

  A hit is registered if $C_n > \mathrm{threshold}$. Timestamps correspond to sample n. A fixed dead-time $T^{\mathrm{dt}}$ is enforced.

• Pulse-Height (Energy) Extraction Four-stage trapezoidal filter with baseline restoration. Final pulse height:

  $$D_{n_0+T^{\mathrm{edelay}}+T^{\mathrm{eint}}}/T^{\mathrm{eint}}$$

• CFD Timing Digital constant-fraction discrimination is applied:

  $$\mathrm{CFD} = \frac{C_n^T}{F^T} - C_{n-T_{\mathrm{tdel}}}^T$$

  Leading to timing precision of ~32 ns (68%) to 174 ns (95%).

• Pile-up/Summing Logic If a second hit occurs within $T^{\mathrm{edif}}$ but after $T^{\mathrm{dt}}$, it is labeled as pile-up: both energies are recovered by shortened integrals. Hits within $T^{\mathrm{dt}}$ are summed as random coincidences.

3. Firmware Algorithms and Event Filtering

• Moving Window Deconvolution for hit detection and digital trapezoidal filtering for energy.
• Configurable Parameters: All critical digital filter windows ($$B_n = \frac{1}{T^{\mathrm{dec}}}\sum_{i=1}^{T^{\mathrm{dif}}}A_{n-i}$$0) are adjustable via web interface.
• Master Filter Logic (in GRIF-C Master): Implements input buffering, event time ordering, optional BGO suppression, detector-type masking, event downscaling, multi-condition coincidence gating (up to 14 conditions), and dispatch to network.

Example (firmware-level) pseudocode of the master filter: $$B_n = \frac{1}{T^{\mathrm{dec}}}\sum_{i=1}^{T^{\mathrm{dif}}}A_{n-i}$$5

4. Data Flow Topology and Performance

The event and data path is fully pipelined with local buffering at each tier, supporting sustained high throughput without global dead-time.

• Data Rates: Each mini-SAS link supports ≈5 Gb/s. No global dead-time; per-channel rates to 50 kHz (demonstrated to 62 kHz).
• Event Building: All GRIF-C Slaves transmit 352-bit raw events to the Master, which time-orders and filters before network export. Input/output FIFOs and DRAM supply deep buffering.
• Master Filter Throughput: 100 million events/s (~35 Gb/s).
• MIDAS Integration: The frontend PC builds disk files from batches of ∼1000 GRIF-16 events per event.

5. Key Performance Metrics and Calibration

• Per-Crystal Max Counting Rate: 50 kHz (tested to 62 kHz), with pile-up recovery maintaining high energy efficiency.
• Energy Resolution:
  • 1.07 keV FWHM at 122 keV (0.88%),
  • 1.87 keV FWHM at 1332 keV (0.14%).
• Timing Resolution:
  • σₜ ≈ 32 ns for 68% of γ–γ coincidences,
  • 95% within 174 ns.
• Relative Efficiency (with pile-up recovery): >80% at 50 kHz, versus ≈45% if pile-up is rejected.
• Peak-to-Total: Constant up to 40 kHz, degrades only above ≈50 kHz.
• System Dead-Time and Traceability: Sub-0.05% uncertainty in half-life/branching-ratio measurements due to rigorous accounting.

Important formulas:

• Energy resolution:

  $$B_n = \frac{1}{T^{\mathrm{dec}}}\sum_{i=1}^{T^{\mathrm{dif}}}A_{n-i}$$1

• Branching ratio uncertainty:

  $$B_n = \frac{1}{T^{\mathrm{dec}}}\sum_{i=1}^{T^{\mathrm{dif}}}A_{n-i}$$2, $$B_n = \frac{1}{T^{\mathrm{dec}}}\sum_{i=1}^{T^{\mathrm{dif}}}A_{n-i}$$3

• Timing uncertainty:

  $$B_n = \frac{1}{T^{\mathrm{dec}}}\sum_{i=1}^{T^{\mathrm{dif}}}A_{n-i}$$4

6. System Integration and Control

• Timing/Sync: GRIF-Clk modules via eSATA, <700 ps skew, <16 ps jitter.
• System Sequencer (GRIF-PPG): 32 LEMO outputs driven by VME state machine for experimental cycle control (beam/tape).
• Adjustability: All critical signal-processing parameters are adjustable live via web-based controls.
• Block Diagrams:
  • Detector → Preamp → GRIF-16/4G → mini-SAS → GRIF-C Slave → mini-SAS → GRIF-C Master → SFP → MIDAS Frontend → Disk.
  • Clock: CSAC Master → eSATA → Slaves → All modules.
  • PPG: GRIF-C Master sequencer → VME → GRIF-PPG → Tape/Beam outputs.

7. Applications, Impact, and Outlook

The Griffin architecture is the enabling digital infrastructure for the GRIFFIN gamma-ray spectrometer, providing the necessary speed, resolution, scaling, and dead-time reliability for advanced decay-spectroscopy research using low-energy radioactive beams. Its design supports:

• Simultaneous operation of up to 64 HPGe channels at high rates.
• Fine-tuned pile-up rejection and recovery critical for high-precision nuclear branching-ratio and half-life measurements.
• Flexible, firmware-driven adaptation to experimental requirements in modern nuclear spectroscopy.
• Sub-0.05% uncertainty in dead-time accounting, supporting next-generation precision measurements (Garnsworthy et al., 2017).

The architecture is cited as an exemplar for fully digital, scalable DAQ systems in multi-detector nuclear physics experiments, and its engineering solutions for synchronization, buffering, and firmware signal processing continue to influence contemporary high-rate spectroscopic DAQ design.