Graphic Parity Network Synthesis

• The Graphic Parity Network Synthesis Problem is defined as converting graph-structured interactions into parity-based circuits via CNOT operations while restoring initial wire states.
• It encompasses multiple formulations—including circuit-theoretic, hypergraph compilation, and QAOA-based methods—that address optimized gate minimization and the mapping of logical graphs to physical hypergraphs.
• The study highlights challenges such as non-uniqueness in inverse synthesis and structural complexity, while proposing algorithms that achieve near-optimal CNOT counts and guarantee unique recovery in specific layouts.

The Graphic Parity Network Synthesis Problem denotes a family of closely related compilation tasks in which graph-structured interactions are transformed into parity-based realizations. In the most direct circuit-theoretic formulation, the input is a graph $G$, the required parities are exactly its edge terms $\{u,v\}$, and the goal is to synthesize a CNOT-only circuit that makes every edge parity appear on some wire while restoring all wires to their original singleton terms with minimum gate count (Cao et al., 12 Sep 2025). A broader parity-architecture formulation treats synthesis as a map from isomorphism classes of logical graphs to families of compiled physical hypergraphs generated from bases of the cycle or constraint space, with emphasis on existence, uniqueness, and inverse recoverability (Dreier et al., 2024). QAOA-oriented work places the same theme in the language of parity supports $S\subseteq \mathbb F_2^n$ for diagonal cost unitaries, while polyhedral work studies exact parity modeling after binarization in graph optimization problems such as the graphic traveling salesman problem (Campbell et al., 2024, Ermel et al., 2018).

1. Formal scope of the problem

In the graph-restricted circuit model, a wire initially carries the singleton term $\{i\}$, and a CNOT gate $cnot(i,j)$ updates the target wire by symmetric difference. If wire $i$ carries $A\subseteq [n]$ and wire $j$ carries $B\subseteq [n]$, then after the gate the target carries $A\oplus B$. For a finite simple graph $\{u,v\}$0 with $\{u,v\}$1, an $\{u,v\}$2-qubit CNOT circuit is a graphic parity network for $\{u,v\}$3 if every edge $\{u,v\}$4 appears as the binary term $\{u,v\}$5 on some wire at some point, and the final wire state is exactly the original state. The size of the network is the number of CNOT gates, and the optimization problem is to minimize that size (Cao et al., 12 Sep 2025).

The parity-architecture formulation is more structural. A hypergraph is $\{u,v\}$6 with $\{u,v\}$7; it is a graph when every edge has size two. The central map is

$\{u,v\}$8

where $\{u,v\}$9 is the set of hypergraph isomorphism classes and $S\subseteq \mathbb F_2^n$0 is the set of all compiled hypergraphs obtained from all bases of the constraint space. The output is therefore not a single layout but a family of admissible compiled hypergraphs, reflecting the fact that different cycle or constraint bases yield different parity compilations (Dreier et al., 2024).

The QAOA-oriented formulation abstracts away from graph topology and works directly with a parity set $S\subseteq \mathbb F_2^n$1 and a terminal linear transformation $S\subseteq \mathbb F_2^n$2. A parity network is then a CNOT-only circuit in which every parity in $S\subseteq \mathbb F_2^n$3 appears as a wire label during the circuit, with $S\subseteq \mathbb F_2^n$4 as the final wire configuration. For the diagonal QAOA setting, the final map is effectively the identity, or a permutation thereof, because the basis must be restored after the diagonal block (Campbell et al., 2024).

These formulations are not identical. One is an edge-parity gate-minimization problem, one is a graph-to-hypergraph compilation problem, and one is a parity-support realization problem over $S\subseteq \mathbb F_2^n$5. What they share is the requirement that prescribed parities be exposed under explicit structural constraints.

2. Algebraic and graph-theoretic foundations

The graph-theoretic formulation in the parity architecture is organized around the edge space, cycle space, and constraint space. For a hypergraph $S\subseteq \mathbb F_2^n$6, the edge space is $S\subseteq \mathbb F_2^n$7, viewed as a vector space over $S\subseteq \mathbb F_2^n$8 with symmetric difference $S\subseteq \mathbb F_2^n$9. For a graph, the cycle space is

$\{i\}$0

where $\{i\}$1 is the set of edge-sets that form cycles. For a hypergraph, the constraint space is

$\{i\}$2

A key identity is that for graphs,

$\{i\}$3

This identifies parity constraints with cycles and makes cycle-space structure the natural invariant for graph-based parity synthesis (Dreier et al., 2024).

Given a basis $\{i\}$4 of the constraint space, the compiled hypergraph $\{i\}$5 is constructed by turning each participating logical edge into a physical vertex and each basis constraint into a physical hyperedge. If

$\{i\}$6

and $\{i\}$7 is an enumeration, then

$\{i\}$8

Thus original pairwise interactions become physical parity variables, while chosen cycles become plaquettes or local parity constraints. The full compilation object is

$\{i\}$9

which depends only on the isomorphism class $cnot(i,j)$0 (Dreier et al., 2024).

The circuit formulation uses the same $cnot(i,j)$1 logic at the wire level. At any moment, the $cnot(i,j)$2 wire labels form a basis of $cnot(i,j)$3, hence an invertible binary matrix. A CNOT updates one basis vector by XORing another into it, so the network traces a path in $cnot(i,j)$4. In the general parity-network setting, a target parity $cnot(i,j)$5 is realized when it appears as one of the current basis vectors. In the graphic case, the required vectors are exactly the incidence vectors of graph edges (Campbell et al., 2024). This yields a three-level distinction that is explicit in the literature: logical graphs encode source interactions, compiled hypergraphs encode physical parity constraints, and wire-label bases encode the transient parities realized by a CNOT circuit.

3. Inverse compilation, preimages, and non-uniqueness

A major question in the parity-architecture literature is inverse synthesis: given a compiled hypergraph or family of layouts, which source graphs could have produced it? The central tool is a loop labeling. For a hypergraph $cnot(i,j)$6, a loop labeling is an injective map

$cnot(i,j)$7

such that each hyperedge, after labeling, lies in the cycle space of an induced graph. Operationally, a loop labeling assigns a candidate logical edge to each physical parity variable so that each compiled plaquette becomes a cycle in some underlying graph (Dreier et al., 2024).

The main preimage theorem states, in effect, that for graph sources the full preimage of a compiled layout family is characterized exactly by admissible loop labelings of one compiled hypergraph $cnot(i,j)$8. The induced graph must have cycle-space dimension equal to the number of basis elements, and the recovered source class must share that cycle space. A corollary gives an alternative form for weakly fundamental bases, namely bases $cnot(i,j)$9 satisfying

$i$0

In that case the preimage description simplifies and imposes additional structure on admissible labelings (Dreier et al., 2024).

Injectivity is then characterized exactly. The parity transformation is injective on a subset $i$1 of graph isomorphism classes if and only if, for every source class in $i$2, there is some representative graph and some cycle basis whose compiled hypergraph admits only one graph class in the corresponding loop-labeling preimage. In practical terms, uniqueness of inverse synthesis is equivalent to uniqueness of the logical graph under all valid loop labelings of the compiled layout (Dreier et al., 2024).

The general picture is negative. The literature gives several explicit counterexamples to injectivity. Adding a new leaf edge that creates no new cycle leaves the cycle space unchanged and therefore leaves the set of compiled hypergraphs unchanged, so graphs that differ by acyclic appendages can compile identically. The ambiguity persists even when every edge lies in a cycle: the paper exhibits two non-isomorphic six-vertex graphs, distinguished for example by degree sequence, with equal compiled hypergraphs under suitable cycle bases. There are also connected higher-dimensional counterexamples: a three-plaquette layout and a seven-plaquette layout each admit two loop labelings that produce non-isomorphic induced graphs of equal cycle-space dimension. The inverse problem is therefore non-unique in general, even after tree ambiguity is removed (Dreier et al., 2024).

4. Uniquely recoverable layouts and exact compilation on rectangular plaquettes

The main positive result on uniqueness concerns rectangular plaquette layouts. A hypergraph $i$3 is a rectangular plaquette layout if there exist integers $i$4 and enumerations

$i$5

$i$6

such that

$i$7

for all admissible $i$8. These are square-grid-like 4-body plaquette hardware layouts (Dreier et al., 2024).

Theorem 4.5 gives a complete existence characterization. There exists a basis $i$9 such that $A\subseteq [n]$0 is a rectangular plaquette layout with $A\subseteq [n]$1 vertical and $A\subseteq [n]$2 horizontal vertices if and only if the cycle-participating restriction

$A\subseteq [n]$3

is a complete bipartite graph with partition sizes $A\subseteq [n]$4 and $A\subseteq [n]$5, where

$A\subseteq [n]$6

The full preimage of this hardware family is therefore exactly the class of graphs whose cyclic core is complete bipartite (Dreier et al., 2024).

Uniqueness follows from a rigidity statement: any two loop labelings of a rectangular plaquette layout produce isomorphic induced graphs. Hence the compiled layout determines a unique logical cycle-space structure up to graph isomorphism. This suggests that what collapses ambiguity is not merely the presence of cycles but the geometric rigidity of the plaquette arrangement.

The same paper gives a polynomial-time compilation procedure for this class. The algorithm first computes $A\subseteq [n]$7 using a spanning forest and the fundamental cycles produced by non-tree edges. It then tests bipartiteness by BFS or DFS, checks completeness of the bipartite core, and, if successful, constructs an explicit 4-cycle basis

$A\subseteq [n]$8

for $A\subseteq [n]$9, with

$j$0

The stated total time complexity is proportional to

$j$1

and correctness follows exactly from the complete-bipartite characterization (Dreier et al., 2024).

5. CNOT-optimal graphic parity networks

The direct minimum-gate problem admits a sharp general lower bound. For any graph $j$2 with $j$3 edges, $j$4 vertices, and $j$5 connected components, every graphic parity network has size at least

$j$6

For connected graphs this becomes

$j$7

The proof rests on a stronger statement: in any graphic parity network for a connected graph, at least $j$8 operations have outcomes that are not binary. Since each required edge must be generated by at least one binary-term-generating operation, the total size is at least $j$9 (Cao et al., 12 Sep 2025).

This lower bound is exact for forests, where $B\subseteq [n]$0 and the optimum is therefore $B\subseteq [n]$1. It is also achieved for a broader exact-minimum class. A graphic parity network of size exactly $B\subseteq [n]$2 is called perfect, and a graph admitting such a network is called perpane. To capture these graphs structurally, the paper defines a perfect cancellation ordering $B\subseteq [n]$3: for every vertex $B\subseteq [n]$4 and every component $B\subseteq [n]$5 of $B\subseteq [n]$6, the set

$B\subseteq [n]$7

must be $B\subseteq [n]$8-linked. Graphs admitting such an ordering are perfect cancellation graphs. Every perfect cancellation graph is perpane, all chordal graphs belong to this class, and given such an ordering one can synthesize a perfect network in linear time. Recognition of perfect cancellation graphs is $B\subseteq [n]$9-complete, but fixed-parameter tractable when parameterized by treewidth. The conjecture that a graph is perpane if and only if it is a perfect cancellation graph remains open (Cao et al., 12 Sep 2025).

The same work proves that some graphs are intrinsically far from perfect. If $A\oplus B$0 has girth at least $A\oplus B$1, then the minimum size is

$A\oplus B$2

Using a projective-plane incidence construction, it obtains $A\oplus B$3-vertex graphs with

$A\oplus B$4

for which every graphic parity network has size

$A\oplus B$5

Thus large-girth graphs are provably resistant to near-perfect cancellation-based synthesis (Cao et al., 12 Sep 2025).

A randomized polynomial-time synthesis algorithm nearly matches this lower bound in important regimes. After processing vertices in a random order, the algorithm exploits already available triangle cancellations, optionally introduces temporary non-edge parities such as $A\oplus B$6 when they help generate many edges, and synthesizes leftovers directly. The expected size is

$A\oplus B$7

and improves to

$A\oplus B$8

when all but a constant number of vertices have degree $A\oplus B$9. For the girth-$\{u,v\}$00 family, this is near-optimal up to the $\{u,v\}$01 factor (Cao et al., 12 Sep 2025).

6. Greedy QAOA-oriented synthesis from graph-derived parity supports

QAOA diagonal synthesis provides a broader but practically important setting for parity-network synthesis. The target unitary is

$\{u,v\}$02

where $\{u,v\}$03 may be an Ising Hamiltonian

$\{u,v\}$04

or a higher-order pseudo-Boolean Hamiltonian with $\{u,v\}$05-body $\{u,v\}$06-products. Because all such diagonal terms commute,

$\{u,v\}$07

factorizes into phase gadgets. If each $\{u,v\}$08-body gadget is synthesized independently, its cost is $\{u,v\}$09 CNOTs, yielding the upper bound

$\{u,v\}$10

where $\{u,v\}$11 is the set of nonzero order-$\{u,v\}$12 terms. The main observation is that a shared parity network can realize many of these parities with substantially fewer CNOTs than separate gadget synthesis (Campbell et al., 2024).

In this formulation, the input is a parity set $\{u,v\}$13. Algorithm 1, Greedy Parity Network Synthesis, repeatedly chooses a remaining target of minimum Hamming weight,

$\{u,v\}$14

selects the two smallest support indices $\{u,v\}$15 and $\{u,v\}$16, applies $\{u,v\}$17, updates every target by the rule

$\{u,v\}$18

and drops any updated target of Hamming weight $\{u,v\}$19, since it has become a basis vector and is therefore realized. Algorithm 2, Greedy Gaussian Elimination or Linear Circuit Inversion, starts from the final basis matrix $\{u,v\}$20 and repeatedly chooses the row pair maximizing

$\{u,v\}$21

then applies a CNOT using the lower-weight row as control until the basis returns to the identity (Campbell et al., 2024).

For diagonal QAOA synthesis, the completed circuit has three layers: a CNOT network that exposes required parities, $\{u,v\}$22 rotations inserted when the relevant parity appears, and a final linear inversion circuit. The paper presents these algorithms as constructive exact synthesis procedures, but does not prove optimality, an approximation ratio, or explicit asymptotic runtime bounds. The intended status is heuristic rather than optimality-certified (Campbell et al., 2024).

The experimental evaluation uses CNOT count as the primary metric and compares against Qiskit default compilation, Qiskit gray-synth, and a hybrid using gray-synth for parity creation and the greedy inversion method for the return path. On random sparse parity sets, both the greedy method and gray-synth outperform Qiskit default compilation as $\{u,v\}$23 grows. On full problems up to order $\{u,v\}$24, the greedy method performs best. On graph-based instances arising from graph coloring on connected caveman graphs, gray-synth performs worst, Qiskit default tracks the greedy method fairly closely at low numbers of cliques, and the greedy method becomes clearly better as clique size increases. The paper is explicit, however, that the algorithms do not exploit graph topology directly; adjacency, separators, treewidth, and local neighborhoods are not part of the synthesis logic. Graph structure enters only through the induced parity support $\{u,v\}$25 (Campbell et al., 2024).

7. Polyhedral formulations, limitations, and open directions

A separate line of work studies parity not as a gate-synthesis target but as a polyhedral modeling primitive. For bounded integer variables $\{u,v\}$26, ordered binarization replaces each variable by

$\{u,v\}$27

The associated ordered even and odd parity polytopes, $\{u,v\}$28 and $\{u,v\}$29, generalize the classical parity polytope. Their complete outer descriptions are expressed through the block parity map

$\{u,v\}$30

which detects odd versus even cardinality inside an ordered block. The resulting generalized forbidden-set inequalities admit a linear-time separation algorithm once the subset structure is fixed (Ermel et al., 2018).

This machinery is applied to the graphic traveling salesman problem. There, edge multiplicities satisfy $\{u,v\}$31, are binarized as

$\{u,v\}$32

and parity over a cut $\{u,v\}$33 yields strengthened blossom inequalities of the form

$\{u,v\}$34

for odd $\{u,v\}$35. The contribution here is exact parity modeling over binarized multiplicity variables rather than a direct network-synthesis algorithm (Ermel et al., 2018).

The same paper gives an important negative result. Applying binarization and only enforcing parity constraints on the new variables is often a bad idea: in the graphic TSP application, parity constraints do not improve the dual bounds. The explanation is encoded by

$\{u,v\}$36

together with a multi-parity condition showing that if $\{u,v\}$37 for each relevant subset $\{u,v\}$38, then one can choose ordered block representations that satisfy both even and odd parity descriptions simultaneously. Exact parity descriptions therefore need not strengthen LP relaxations unless the binarized variables are more tightly integrated into the rest of the model (Ermel et al., 2018).

Across the current literature, several limitations remain explicit. The parity-architecture theory provides a rigorous preimage characterization and an exact polynomial-time compiler for rectangular plaquette layouts, but does not give a full general-purpose synthesis algorithm for arbitrary target layouts or a general complexity classification of the broader compilation problem (Dreier et al., 2024). The QAOA-oriented greedy methods are logically exact in intent and empirically effective, but they remain heuristics without formal optimality guarantees and do not model hardware connectivity or routing (Campbell et al., 2024). The graph-restricted minimum-CNOT theory establishes strong lower bounds, near-optimal randomized synthesis, and an exact-minimum class with nontrivial structure, yet the conjectured characterization of all perpane graphs is unresolved and recognition of the known structural class is already $\{u,v\}$39-complete (Cao et al., 12 Sep 2025). A plausible implication is that the field now separates into three regimes: rigid layout classes with exact recoverability, general parity-support instances where heuristic circuit synthesis dominates, and parity-constrained integer formulations where exact polyhedral descriptions do not automatically yield stronger relaxations.