The paper presents FEATHer as a state-of-the-art model delivering accurate long-range forecasts on edge devices using as few as 400 parameters.
It employs a multiscale decomposition with a shared Dense Temporal Kernel and frequency-aware gating to efficiently process different signal frequencies.
Experimental results show FEATHer outperforms benchmarks across diverse time-series datasets while maintaining ultra-low latency and memory usage.
The Fourier-Efficient Adaptive Temporal Hierarchy Forecaster (FEATHer) is a time-series forecasting architecture designed for accurate long-term predictions on severely resource-constrained edge devices, such as programmable logic controllers and microcontrollers. FEATHer achieves state-of-the-art long-range forecasting accuracy with as few as 400 parameters by combining hand-crafted yet learnable multiscale decomposition, a shared depthwise convolutional temporal mixer, adaptively fused frequency-aware pathway gating, and a sparse, parameter-minimal period extrapolation kernel. Its design is motivated by the need to meet millisecond-level latency and minimal memory usage requirements in industrial and cyber-physical systems, where conventional deep sequence models are often infeasible due to hardware limitations (Lee et al., 16 Jan 2026).
1. Multiscale Input Decomposition with Frequency Pathways
FEATHer decomposes the input sequence X∈RL×D into four parallel, time-aligned branches, each focused on a distinct frequency band:
Point branch (b=p):kp=1
X(p)=DWConvk=1(InstanceNorm(X))
High-frequency branch (b=h):kh=3
X(h)=DWConvk=3(InstanceNorm(X))
Mid-frequency branch (b=m):km=5
X(m)=DWConvk=5(InstanceNorm(X))
Low-frequency branch (b=l): Downsample then upsample
X(l)=UpsampleL(AvgPoolr(InstanceNorm(X))), r=4
Each branch’s kernel is implemented as a depthwise 1D convolution. The low-frequency branch employs stride-based average pooling followed by linear upsampling to filter out high-frequency content with no learnable parameters, resulting in a near-orthogonal filter bank that reduces cross-frequency interference under extreme parameter constraints. All pathway outputs maintain sequence length L, easing later fusion.
2. Shared Dense Temporal Kernel for Lightweight Temporal Modeling
After multiscale decomposition, each branch is processed by a shared Dense Temporal Kernel (DTK), which performs “projection–depthwise convolution–reverse projection” to maintain parameter efficiency:
Linear projection:kp=10, kp=11
Depthwise temporal convolution:kp=12, operates independently on each channel, kp=13 typically 3 or 5
Reverse (output) projection:kp=14, kp=15
Weights kp=16 are shared across all branches, so total parameter count does not scale with the number of frequency bands. The construction is proven globally Lipschitz with constant at most kp=17.
3. Frequency-Aware Branch Gating
FEATHer adapts the fusion of branch outputs via instance-dependent, spectrum-driven gating. The gating process is as follows:
The fused representation is X(p)=DWConvk=1(InstanceNorm(X))4, X(p)=DWConvk=1(InstanceNorm(X))5, where X(p)=DWConvk=1(InstanceNorm(X))6 is the number of branches. The energy-based gating is derived by entropy-regularized cross-entropy minimization, resulting in a softmax policy X(p)=DWConvk=1(InstanceNorm(X))7, where X(p)=DWConvk=1(InstanceNorm(X))8 is the relevance (“energy”) of branch X(p)=DWConvk=1(InstanceNorm(X))9.
4. Sparse Period Kernel for Forecast Projection
To efficiently map latent states to multistep output forecasts (kh=30), the Sparse Period Kernel (SPK) is used:
Phase-alignment: Choose period kh=33 such that kh=34 divides kh=35 and kh=36. For each channel, reshape kh=37 to kh=38, with kh=39, X(h)=DWConvk=3(InstanceNorm(X))0
Shared linear mapping: For each phase X(h)=DWConvk=3(InstanceNorm(X))1, X(h)=DWConvk=3(InstanceNorm(X))2, with X(h)=DWConvk=3(InstanceNorm(X))3 shared across channels
Recombine: Interleave all X(h)=DWConvk=3(InstanceNorm(X))4 outputs to form X(h)=DWConvk=3(InstanceNorm(X))5
SPK is shown to be parameter-minimal; for phase-aligned period mappings, at least X(h)=DWConvk=3(InstanceNorm(X))6 parameters are necessary and SPK uses exactly X(h)=DWConvk=3(InstanceNorm(X))7.
5. Parameter Efficiency, Memory, and Computational Characteristics
The FEATHer model can be instantiated with as few as X(h)=DWConvk=3(InstanceNorm(X))8 trainable parameters:
Decomposition filters: Negligible (fixed, depthwise conv and pooling)
Dense Temporal Kernel:X(h)=DWConvk=3(InstanceNorm(X))9 (projection matrices and conv)
Sparse Period Kernel:km=50
For a typical “ultra-compact” configuration: km=51 (univariate), km=52, km=53, km=54, km=55, the SPK uses km=56 parameters, and the total is km=57. Peak RAM usage is km=58 KB for km=59, X(m)=DWConvk=5(InstanceNorm(X))0, and X(m)=DWConvk=5(InstanceNorm(X))1 KB for moderate X(m)=DWConvk=5(InstanceNorm(X))2. Inference cost is X(m)=DWConvk=5(InstanceNorm(X))3 per step, all terms linear in X(m)=DWConvk=5(InstanceNorm(X))4 and X(m)=DWConvk=5(InstanceNorm(X))5. On ARM Cortex-M3, latency per X(m)=DWConvk=5(InstanceNorm(X))6 forecast varies from X(m)=DWConvk=5(InstanceNorm(X))7 ms to X(m)=DWConvk=5(InstanceNorm(X))8 ms.
6. Experimental Results and Comparative Evaluation
FEATHer was evaluated on eight long-range multivariate time-series benchmarks:
Metrics include mean squared error (MSE), mean absolute error (MAE), and Pearson correlation (COR). FEATHer attained the best ranking in 60 cases (across 8 datasets and 4 horizons), with an average rank of X(m)=DWConvk=5(InstanceNorm(X))9 versus X(l)=UpsampleL(AvgPoolr(InstanceNorm(X)))0–X(l)=UpsampleL(AvgPoolr(InstanceNorm(X)))1 for the next best baseline. On Solar-Energy, X(l)=UpsampleL(AvgPoolr(InstanceNorm(X)))2 horizon, FEATHer’s MSE was X(l)=UpsampleL(AvgPoolr(InstanceNorm(X)))3 compared to PatchTST’s X(l)=UpsampleL(AvgPoolr(InstanceNorm(X)))4, but FEATHer used X(l)=UpsampleL(AvgPoolr(InstanceNorm(X)))5K parameters whereas PatchTST used X(l)=UpsampleL(AvgPoolr(InstanceNorm(X)))6M. Ablation studies demonstrated that each core FEATHer component contributed a X(l)=UpsampleL(AvgPoolr(InstanceNorm(X)))7–X(l)=UpsampleL(AvgPoolr(InstanceNorm(X)))8 improvement in MSE.
7. Deployment Implications for Edge Inference
FEATHer’s architectural minimalism enables real-time deployment on microcontrollers and PLCs. On ARM Cortex-M3, inference latency (for X(l)=UpsampleL(AvgPoolr(InstanceNorm(X)))9) is r=40 ms, rising to r=41–r=42 ms for r=43. Peak RAM usage is r=44 KB for single-channel input, and r=45 KB for eight-channel cases. For comparison, transformer models require r=46–r=47 KB activations and r=48 ms latency. This resource profile satisfies stringent requirements in industrial automation, embedded control, and energy-constrained settings, where on-chip SRAM and sub-millisecond latency are indispensable (Lee et al., 16 Jan 2026). A plausible implication is that FEATHer’s approach provides a template for scalable, data-efficient forecasting in safety-critical cyber-physical systems operating with on-chip resources.
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