CMOS Coupled Oscillator-Based Ising Machine (COBI)

• COBI is a hardware platform that uses coupled CMOS oscillators and sub-harmonic injection locking to physically minimize an Ising Hamiltonian.
• It leverages mature CMOS technology to achieve rapid convergence (ns–ms) and low energy consumption for NP-hard tasks like MAX-CUT and MIMO detection.
• Experimental and simulation results highlight its scalability, robust performance under noise, and effective programmable coupling implementations.

A CMOS Coupled Oscillator-Based Ising Machine (COBI) utilizes arrays of CMOS oscillators, interconnected through programmable couplings and enforced by sub-harmonic injection locking, to physically implement the minimization of an Ising Hamiltonian. Information is encoded in binary phase relationships among oscillators, such that the emergent collective state after transient dynamics represents the solution to NP-hard problems such as MAX-CUT, partitioning, coloring, or certain machine learning tasks. COBI leverages mature CMOS technology for device fabrication, dense integration, low energy, and real-time parallel computation. Recent experimental and simulated systems demonstrate COBI’s viability for combinatorial optimization, neuromorphic inference, and embedded inference in diverse domains.

1. Physical and Mathematical Foundation

The COBI paradigm is rooted in the collective phase dynamics of coupled nonlinear CMOS oscillators, typically implemented as ring or LC oscillators with tailored phase response functions. The core model is the generalized Kuramoto phase evolution with a sub-harmonic injection locking (SHIL) term: $$\dot{\theta}_i = \omega_i + \sum_j K_{ij} \sin(\theta_j - \theta_i) + I \sin(2\theta_i - \phi_{\mathrm{SHIL}})$$ where $\theta_i$ is the phase of the $i$-th oscillator, $\omega_i$ its intrinsic frequency, $K_{ij}$ the coupling coefficient (proportional to conductance between oscillators), and $I$ the SHIL amplitude (enforcing bistability at $\theta_i\in\{0,\pi\}$). This dynamic admits a Lyapunov function

$H(\phi) = -\sum_{i<j} J_{ij} \cos(\phi_i - \phi_j)$

with $J_{ij}$ mapped from the physical edge weights, and the binary Ising representation

$$\sigma_i = \begin{cases} +1, & \phi_i \approx 0 \ -1, & \phi_i \approx \pi \end{cases}$$

The physical evolution naturally solves for spin configurations minimizing $H$, so long as the SHIL amplitude is correctly chosen to binarize the phases (Roy et al., 5 Feb 2025, Wang et al., 2019, Wang et al., 2019).

2. CMOS Architectural Realization

COBI designs exploit two primary oscillator implementations: LC tanks (with spiral inductors/MIM capacitors, cross-coupled inverter pairs) or ring oscillators (chains of odd-numbered CMOS inverters, enabling GHz operation in fine lithographies). Couplings $J_{ij}$ are realized by digitally or analog-programmable resistive/capacitive elements (MOSFETs in triode, DACs, or nonvolatile memory devices such as FeFETs) in crossbar configurations, with supporting topologies enabling full connectivity or scalable sparsity (Jadia et al., 1 Nov 2025, Gonul et al., 5 Apr 2025, Kumar et al., 26 Feb 2025). SHIL is delivered via on-chip frequency-multiplied tone generators, with clock distribution, preferably using distributed injection to minimize phase error and locking time (Vosoughi, 2020). Readout is performed via digital phase detectors (XOR, sense amplifiers, or SAR logic), and power integrity is maintained by local decoupling capacitors and guard rings.

Typical device parameters:

• Oscillator core: $f_0$ = $100\,\mathrm{MHz}$–$7\,\mathrm{GHz}$; $V_{\mathrm{DD}}$ = $1$–$1.2\,\mathrm{V}$; per-core area $<0.01\,\mathrm{mm}^2$
• Coupling weights: 5–10 bit programmable resolution; conductance range $1$–$60\,\mu\mathrm{S}$ (FeFET); resistance $10\,\mathrm{k}\Omega$–$100\,\mathrm{k}\Omega$ (MOS, DAC, digipot)
• SHIL network: 2–3$\times f_0$; lock range $\pm 5\%f_0$; distributed injection for uniform $\kappa_s$
• Power: Sub-$1\,\mathrm{mW}$ per oscillator; full arrays scale linearly (Chou et al., 2019, Gonul et al., 5 Apr 2025)

3. Information Encoding, Problem Mapping, and Solution Dynamics

Logical spins ($+1/–1$ for Ising machine) are encoded in the stable phase states. The Ising Hamiltonian is programmed by setting the physical inter-oscillator coupling strengths and bias fields. For weighted problems, multi-bit resistance/conductance values are mapped linearly to $J_{ij}$, with sign set by crossbar selection.

Typical mapping:

• MAX-CUT: antiferromagnetic $J_{ij}=-\mu_{ij}$ (graph weight)
• MIMO symbol decoding: quadratic/field coefficients map to conductances/biases (Jadia et al., 1 Nov 2025)
• Extractive summarization: select-$k$ constraints encoded via auxiliary penalty terms and bias scaling, followed by quantization and stochastic rounding (Zeng et al., 16 Jan 2026)

Operational protocol:

1. Initialize: Oscillators uncoupled, randomize phases
2. Program couplings ($J_{ij}$) and biases ($h_i$)
3. Enable coupling and SHIL; allow $\sim$5–100 cycles for convergence (Roy et al., 5 Feb 2025)
4. Readout: digital phase detector yields spin configuration
5. Optional: apply noise and annealing schedules (coupling/SHIL ramps) to enhance ground-state solution probability (Wang et al., 2019)

4. Experimental Results, Performance, and Benchmarks

Bench-scale and simulated COBI systems exhibit rapid ms–ns-scale convergence, high single-run ground state probability, and energy consumption scaling in the $\mu$J–nJ regime per solve.

Key metrics:

• Convergence time: $5$–$70$ cycles ($1\,\mathrm{ms}@3.8\,\mathrm{kHz}$ to $10\,\mathrm{ns}@7\,\mathrm{GHz}$)
• Solution quality: $>90\%$ correct MAX-CUT or coloring for well-tuned couplings; $98\%$ accuracy for binary weights, $84\%$ for 5-bit (Chou et al., 2019, Roy et al., 5 Feb 2025, Gonul et al., 5 Apr 2025)
• Scaling: Logarithmic time growth up to $100\times100$ spins in MIMO detection; competitive against brute-force, Tabu search, and simulated annealing (Jadia et al., 1 Nov 2025, Zeng et al., 16 Jan 2026)
• Power: prototype analog modules $10\,\mathrm{mW}$/oscillator, CMOS targets $<1\,\mathrm{mW}$; total consumption scales linearly or sub-linearly (Gonul et al., 5 Apr 2025)
• Energy-to-solution: $100$–$200\,\mu$J (1k spin, $1\,\mathrm{ms}$), $0.2$–$0.6$ mJ for extractive summarization, two to three orders of magnitude below digital alternatives (Zeng et al., 16 Jan 2026)

5. Robustness, Noise, and Device Variability

COBI performance is resilient to moderate phase noise, limited phase response curve non-uniformity, and 10-bit quantization artifacts. Techniques for performance enhancement include:

• Controlled noise injection (Gaussian, jitter) for annealing and trapping escape
• Distributed SHIL for uniform phase locking and minimized error; observed $219.8\%$ increase in convergence speed, $53.6\%$ reduction in phase error (Vosoughi, 2020)
• Precision rebalance (auxiliary bias addition) and stochastic rounding to offset scale imbalances under coefficient quantization (Zeng et al., 16 Jan 2026)
• Hardware calibration: on-chip PLL, varactor arrays, closed-loop conductance adjustment
• Readout error minimized by digital phase detection at reference, typically via XOR or time-to-digital converter (Wang et al., 2019, Gonul et al., 5 Apr 2025)

6. Scalability, Integration, and Future Directions

Scalability is constrained primarily by coupling network complexity ($O(N^2)$ for all-to-all), power and area budgets, and limited precision on programmable couplers. Solutions include adaptation to sparse or hierarchical coupling, modular tileable networks, 3D integration (e.g., FeFET crossbars over oscillator substrate), frequency-/code-division multiplexing for dense interconnect, and high-precision digital-analog hybrid control.

Emergent research directions:

• Development of ternary/multivalued phase architectures (Potts machines)
• Robust annealing schedules (K-ramp, SHIL ramp)
• Integration of on-chip learning circuits (Equilibrium Propagation with local update logic, as in recent high-accuracy MNIST demonstrators)
• Embedded applications: ultra-fast wireless symbol decoding, near real-time extractive summarization
• Adaptive problem decomposition and rounding schemes for large-scale optimization with stringent hardware constraints (Zeng et al., 16 Jan 2026)

7. Applications and Significance

COBI machines have achieved competitive results in combinatorial optimization (MAX-CUT, graph coloring, partitioning), neuromorphic learning (MNIST classification), MIMO symbol detection, and real-time text summarization. The technology promises sub-ms to ns time-to-solution at nJ–mJ energy budgets, straightforward integration in modern CMOS processes, and co-design options for customized pipeline deployment in edge inference (Roy et al., 5 Feb 2025, Zeng et al., 16 Jan 2026, Gower, 4 May 2025).

COBI constitutes a well-articulated hardware platform for analog energy minimization, distinguished by dense phase-state encoding, dynamic parallelism, low power, and compatibility with scalable VLSI architectures. The field continues to evolve toward higher precision, improved robustness, large-array integration, and deployment in application-specific inference and optimization engines.