Error-Correcting Splat Addition

• Error Correcting Splat Addition is a fault-tolerant reversible one-bit adder implemented via the [[8,3,2]] colour code on a quantum processor.
• The method leverages transversal non-Clifford (ccz) operations and optimized state preparation/measurement, reducing two-qubit gate overhead and error susceptibility.
• Comparisons with surface-code architectures highlight its dramatic reduction in gate count and fault pair vulnerabilities, making it practical on current hardware.

“Error-correcting splat addition” may be understood, in the present context, as an Editor's term for the fault-tolerant implementation of one-bit addition using the $[[8,3,2]]$ colour code on the Quantinuum H1-1 quantum computer. The underlying result is a reversible one-bit classical addition circuit implemented on a quantum computer and executed fault-tolerantly with a transversal non-Clifford gate, low-overhead preparation and measurement routines, and the deliberate omission of unnecessary error-correction gadgets. In the reported experiment, the encoded computation uses the smallest colour code that supports a useful transversal $ccz$, protects exactly three logical qubits, and yields an observed arithmetic error rate of $0.11 \pm 0.07\%$ on hardware, compared with $0.95 \pm 0.19\%$ for the corresponding unencoded circuit (Wang et al., 2023).

1. Computational task and reversible formulation

The implemented task is described as “one-qubit addition,” but it is more precisely a reversible one-bit classical addition circuit realized on a quantum processor. Classically, adding two bits $a$ and $b$ produces a two-bit sum $s=s_1 s_0$, and the logical circuit maps

$$|a\rangle |b\rangle |0\rangle \mapsto |a\rangle |s_1\rangle |s_0\rangle.$$

Because ordinary addition is not reversible, the transformation requires a third bit or qubit to store the carry information and thereby remain unitary (Wang et al., 2023).

To make the experiment genuinely quantum rather than merely a classical reversible computation, the inputs are chosen as $|+\rangle|+\rangle$ rather than computational basis states. This prepares the uniform superposition of all valid one-bit sums, after which one outcome is measured. In the logical circuit used for the remainder of the experiment, the Toffoli is replaced by a $ccz$ gate conjugated by Hadamards, and after simplification the process becomes the “superposition” circuit

$ccz$0

This formulation is significant because it embeds a computationally meaningful arithmetic primitive in a short quantum algorithm whose correctness can be checked operationally. A plausible implication is that the task was selected not for algorithmic scale but because it exercises precisely the ingredients needed to demonstrate complete fault-tolerant computation in a minimal setting.

2. Code structure: the $ccz$1 colour code

The encoding uses the $ccz$2-qubit colour code, written as the $ccz$3 code, where the notation denotes 8 physical qubits, 3 logical qubits, and distance 2. It is described as the “smallest interesting colour code” because it is the smallest code that supports a transversal non-Clifford gate useful for universal computation, namely $ccz$4. The code protects three logical qubits, exactly matching the resource requirement of one-bit addition (Wang et al., 2023).

The stabilizer table and logical-operator layout exhibit a cube geometry. Within this geometry, the logical $ccz$5 is transversal, and the logical operators are arranged so that some logical gates can be implemented by simple permutations of physical qubits. The appendix also gives a useful relation to a $ccz$6 code for Hadamard-teleportation constructions, although the main experiment uses the $ccz$7-qubit colour code directly.

The central architectural consequence is that the code’s logical structure aligns unusually well with the target computation. Non-Clifford computation is handled natively through transversality, while some Clifford operations reduce to relabelling or transport. This is the basis for what the paper characterizes as an “inversion of difficulty”: operations that are physically noisy, such as CNOT and $ccz$8, are implemented fault-tolerantly via permutation and transversality, whereas preparation and measurement consume most of the circuit budget.

3. Low-overhead fault-tolerant methodology

A defining methodological choice is the omission of unnecessary QEC circuits. Rather than following the standard “prepare, error-correct, operate, error-correct, measure” pattern from threshold proofs, the implementation keeps only the components needed to detect the dominant faults for this short computation. This reduction in gadget overhead is identified as one of the main reasons the final fault-tolerant circuit is small enough for contemporary hardware (Wang et al., 2023).

For state preparation, the protocol fault-tolerantly prepares $ccz$9 in the $0.11 \pm 0.07\%$0 colour code. A conventional CSS-code method would require measuring $0.11 \pm 0.07\%$1-stabilizers in multiple rounds and, for this $0.11 \pm 0.07\%$2 code, would take about 32 CNOTs and 8 measurements. Instead, a Goto-style circuit-design approach is used: a short non-fault-tolerant entangling circuit is first constructed, and only the stabilizer measurements needed to detect dangerous high-weight propagated errors are added. The circuit is verified via breadth-first search over canonical stabilizer states. The resulting preparation circuit requires 18 CNOTs and 2 measurements, roughly halving the two-qubit-gate cost relative to the generic approach.

For measurement, the experiment uses a low-overhead destructive logical $0.11 \pm 0.07\%$3 measurement. In a generic CSS procedure, all data qubits would be measured in the $0.11 \pm 0.07\%$4 or $0.11 \pm 0.07\%$5 basis and the logical eigenvalues reconstructed from classical parities, but that generic method cannot simultaneously access the required mixed $0.11 \pm 0.07\%$6- and $0.11 \pm 0.07\%$7-type observables. In the $0.11 \pm 0.07\%$8 code, a logical $0.11 \pm 0.07\%$9 supported on one face of the cube can instead be measured destructively by directly measuring those four qubits in the $0.95 \pm 0.19\%$0 basis. This leaves the remaining two logical qubits in a $0.95 \pm 0.19\%$1 code structure. Because this destructive measurement is not fully fault-tolerant by itself, it is supplemented by a flag-based non-destructive measurement of $0.95 \pm 0.19\%$2 on the opposite face, and the parity of five measurement outcomes is used to reconstruct the stabilizer eigenvalue $0.95 \pm 0.19\%$3.

This methodology does not implement full-fledged error correction after every logical step. Instead, it detects the most consequential faults for a computation of limited depth. This suggests a design philosophy in which fault tolerance is tailored to the concrete algorithm and hardware rather than inherited wholesale from asymptotic threshold constructions.

4. Logical gate realization and hardware mapping

The entangling logical operation used in the addition circuit includes a logical CNOT implemented “by permutation.” Because the $0.95 \pm 0.19\%$4 code possesses a spatial symmetry not shared by all logical operators, reflecting or relabelling qubits acts as a logical CNOT. On the Quantinuum H1-1 ion-trap QCCD architecture, physical qubits can be transported between zones, so this logical CNOT is realized with essentially unit-fidelity transport operations rather than noisy entangling gates (Wang et al., 2023).

The non-Clifford component is the transversal $0.95 \pm 0.19\%$5 gate. In the implementation, this transversal $0.95 \pm 0.19\%$6 acts directly on the three encoded logical qubits, so the computation uses the code’s intrinsic non-Clifford transversality instead of magic-state distillation or gate teleportation. This is presented as a major conceptual departure from conventional fault-tolerant quantum computing, where codes are often optimized for Clifford operations and then incur large overhead for non-Clifford synthesis.

At the logical-circuit level, the full fault-tolerant one-bit adder uses 24 CNOTs and 12 measurements. After compilation and the use of transport and permutation simplifications, the implemented fault-tolerant circuit contains only 36 error-prone two-qubit gates and measurements in total. The corresponding bare, unencoded circuit uses 5 CNOTs and 3 measurements.

The hardware significance is therefore not merely that a logical algorithm was executed, but that code symmetry and trapped-ion transport were leveraged to replace otherwise error-prone logical operations with operations that are nearly free in hardware terms. A plausible implication is that the utility of very small colour codes depends strongly on architectures where permutation-like logical actions can be implemented with negligible additional noise.

5. Error metric, simulation support, and observed performance

The experiment defines an “arithmetic error” operationally by checking whether the measured output $0.95 \pm 0.19\%$7 is a valid one-bit sum. A run is counted as erroneous when the condition

$0.95 \pm 0.19\%$8

fails. This operational metric is used instead of full three-qubit process tomography, which would have substantially higher sampling cost and would incorporate SPAM errors in a less convenient way (Wang et al., 2023).

The paper supports this metric with a density-matrix simulation using a noise model motivated by the H1-1 emulator. In that simulation, the arithmetic error rate is $0.95 \pm 0.19\%$9, and the final simulated state fidelity is $a$0, suggesting that arithmetic error is a meaningful proxy for logical failure in this setting.

The reported quantitative results are summarized below.

Implementation	Arithmetic error rate	Additional detail
Fault-tolerant circuit on the H1-1 device	$a$1	8998 post-selected shots
Fault-tolerant circuit on the emulator	$a$2	88,537 post-selected shots
Unencoded circuit on the H1-1 device	$a$3	—
Unencoded circuit on the emulator	$a$4	—

The table in the paper further shows that the valid outputs appear with near-uniform probabilities around $a$5 each, whereas invalid outputs are suppressed much more strongly in the fault-tolerant implementation. The post-selection overhead is reported as moderate, about $a$6, since only runs satisfying the fault-detection conditions contribute to the fault-tolerant arithmetic-error estimate.

Within the limits of the chosen metric, these data show that the encoded computation outperforms the bare circuit on the same hardware. The result is especially notable because the encoded implementation remains experimentally small despite using active fault-detection structure.

6. Comparison with surface-code-style realizations and broader significance

The paper compares the $a$7 realization with planar or surface-code-style architectures for the same arithmetic task. It estimates that a distance-2 surface-code implementation would be dominated by a $a$8 magic-state factory requiring 18 surface-code patches, or about $a$9 physical qubits at $b$0. By contrast, the $b$1 implementation is much smaller and can be executed on an H-series trapped-ion machine (Wang et al., 2023).

The comparison is sharpened by a count of “malicious fault pairs.” The reported numbers are 84,873 for the $b$2 surface-code version and 1,116 for the $b$3-code implementation, indicating substantially lower second-order fault susceptibility in the latter setting for this task.

The stated significance of the result is that it demonstrates a complete fault-tolerant algorithm rather than an isolated gate or memory experiment. Earlier milestones in experimental fault tolerance often addressed ingredients separately, such as memory gadgets, entangling gates, or magic-state preparation. Here, the experiment combines transversal non-Clifford computation, logical Clifford operations by permutation, low-overhead fault-tolerant preparation and measurement, and the intentional omission of unnecessary error-correction gadgets in a single working computation.

A common misconception would be to treat the demonstration as equivalent to a scalable universal fault-tolerance architecture. The paper does not make that claim. Instead, it shows that the $b$4 colour code is not merely a theoretical curiosity but a practical near-term platform for error-correcting arithmetic, and that a fault-tolerant one-bit adder can outperform the corresponding bare circuit in observed arithmetic error rate with remarkably small experimental overhead. This suggests that small-code, task-specific fault-tolerant design can be experimentally competitive when code symmetries, native transversality, and hardware transport capabilities are carefully aligned.