CIM-Tuner Optimization Frameworks

• CIM-Tuner is an optimization framework with dual interpretations, used for hyperparameter tuning in Coherent Ising Machines and for hardware-mapping co-exploration in SRAM accelerators.
• It employs sequential single-parameter tuning with a portfolio of optimizers to overcome high-dimensional challenges and reduce Time To Solution in combinatorial problems.
• In the SRAM-CIM context, CIM-Tuner integrates hardware configuration and layer mapping under area constraints, significantly enhancing throughput and energy efficiency.

Searching arXiv for the relevant CIM-Tuner papers to ground the article and disambiguate the term. CIM-Tuner is a name used for two distinct optimization frameworks in contemporary arXiv literature. In one usage, it denotes a portfolio-based hyperparameter-tuning framework for the Chaotic Amplitude Control with momentum (CACm) algorithm in Coherent Ising Machines (CIMs), where the objective is to minimize Time To Solution (TTS) by decomposing a five-dimensional hyperparameter search into sequential one-dimensional subproblems (Hanyu et al., 27 Jul 2025). In a second usage, it denotes an automatic co-exploration tool for SRAM Computing-In-Memory (CIM) accelerators that jointly balances hardware configuration and layer-wise mapping strategy under an area constraint, targeting throughput or energy efficiency (Chen et al., 26 Jan 2026). A related but differently named framework, CQ-CiM, has also been described as acting as a “CiM-Tuner” for hardware-aware embedding shaping in retrieval systems, but it is not itself titled CIM-Tuner (Li et al., 23 Feb 2026).

1. Terminological scope and disambiguation

The term CIM-Tuner is not unique to a single research line. It appears in at least two technically separate contexts.

Paper	Domain	Core objective
"Towards Generalized Parameter Tuning in Coherent Ising Machines: A Portfolio-Based Approach" (Hanyu et al., 27 Jul 2025)	Coherent Ising Machines	Hyperparameter tuning of CACm via sequential single-parameter optimization
"CIM-Tuner: Balancing the Compute and Storage Capacity of SRAM-CIM Accelerator via Hardware-mapping Co-exploration" (Chen et al., 26 Jan 2026)	SRAM Computing-In-Memory accelerators	Joint hardware balancing and mapping optimization under area constraint

In the first meaning, the framework addresses algorithmic sensitivity in CIM-based combinatorial optimization. The starting observation is that CACm, described as “one of the most accurate solvers on Coherent Ising Machines (CIMs),” is “notoriously sensitive to a high-dimensional set of hyperparameters,” and simultaneous tuning by a single black-box optimizer can be ineffective because of the curse of dimensionality (Hanyu et al., 27 Jul 2025).

In the second meaning, the framework addresses accelerator design and deployment. Here the central problem is the trade-off, under a fixed silicon area budget, between allocating area to the CIM macro array and allocating area to on-chip Input/Output SRAM buffers. Excess compute area can induce frequent off-chip transfers and stalls, whereas excess storage area can reduce peak MAC throughput and under-utilize compute (Chen et al., 26 Jan 2026).

A common source of confusion is therefore lexical rather than technical: the same name labels frameworks for two different meanings of “CIM,” namely Coherent Ising Machines and Computing-In-Memory. This suggests that the term should always be interpreted with its surrounding research context.

2. CIM-Tuner for Coherent Ising Machines

In the Coherent Ising Machine setting, CIM-Tuner is a hyperparameter-tuning framework for the Chaotic Amplitude Control with momentum (CACm) algorithm. It takes as input a baseline parameter vector

$P_0 = (\beta_1, \beta_2, \alpha, \gamma, \xi),$

where $\beta_1$ and $\beta_2$ control the decaying damping rate, $\alpha$ is the coupling strength, $\gamma$ the momentum coefficient, and $\xi$ the auxiliary-variable update rate in CACm (Hanyu et al., 27 Jul 2025).

The optimization goal is

$$\min_P TTS(P) \quad \text{subject to} \quad p_i \in [L_i, U_i], \; i=1,\ldots,5,$$

with the formal statement

$$P^* = \arg \min_{P \in D_1 \times \cdots \times D_N} TTS(P).$$

The domains are given as

$$\beta_1,\beta_2 \in [0,2], \qquad \alpha,\gamma \in [0,2], \qquad \xi \in [0,0.3].$$

The TTS objective is defined by

$TTS(P) = \frac{\log(1 - 0.99)}{\log(1 - P_0(P))},$

where $\beta_1$0 is the empirical probability that a single CACm run with parameters $\beta_1$1 reaches the ground state, and the constant $\beta_1$2 prescribes 99% reliability (Hanyu et al., 27 Jul 2025).

The framework is motivated by the observation that tuning all CACm parameters simultaneously using a single black-box optimizer, including Bayesian Optimization via TPE, “suffers from the curse of dimensionality: even hundreds of trials fail to yield significant gains” (Hanyu et al., 27 Jul 2025). CIM-Tuner remedies this by two mechanisms: partitioning the tuning problem into a sequence of one-dimensional subproblems, and embedding a small portfolio of search strategies—TPE, GP, CMA-ES, Random, and Grid—that can be dynamically switched according to each parameter’s characteristics (Hanyu et al., 27 Jul 2025).

The underlying CACm dynamics are also specified. The algorithm evolves a continuous state $\beta_1$3 and an auxiliary vector $\beta_1$4 over $\beta_1$5 time steps. The time-dependent damping is

$\beta_1$6

At each step,

$\beta_1$7

$\beta_1$8

where $\beta_1$9 is the fixed step-size and $\beta_2$0 with $\beta_2$1 the Ising-coupling matrix. The final spin configuration is $\beta_2$2 (Hanyu et al., 27 Jul 2025).

This formulation makes the role of CIM-Tuner highly specific: it is not a new solver for the Ising Hamiltonian itself, but an auto-tuning layer for a solver whose performance depends strongly on hyperparameter choice.

3. Sequential and screened tuning methods in the CIM setting

The Coherent Ising Machine version of CIM-Tuner is instantiated as Method A and Method B.

Method A is described as Sequential Single-Parameter Tuning. It cycles through the $\beta_2$3 hyperparameters in a fixed user-specified order—reported experimentally as $\beta_2$4—and dedicates an equal share $\beta_2$5 of the total budget $\beta_2$6 to each (Hanyu et al., 27 Jul 2025). At step $\beta_2$7, all parameters except $\beta_2$8 are fixed at their most recently optimized values, and the optimizer portfolio component $\beta_2$9 proposes the next value of $\alpha$0.

The procedure is given as:

$\alpha$1

for $\alpha$2,

$\alpha$3

then

$\alpha$4

and finally it returns $\alpha$5 and $\alpha$6 (Hanyu et al., 27 Jul 2025).

Method B augments Method A with an initial screening phase. With an initial budget $\alpha$7 per parameter, it independently optimizes each $\alpha$8 for $\alpha$9 trials and measures the temporary TTS decrease

$\gamma$0

These $\gamma$1 values are sorted in descending order to produce a priority sequence $\gamma$2, and Method A is then applied on this reordered list using the remaining budget $\gamma$3 (Hanyu et al., 27 Jul 2025).

The procedure is stated as:

$\gamma$4

for $\gamma$5,

$\gamma$6

$\gamma$7

then define $\gamma$8 so that

$\gamma$9

and call Method A with the reordered parameter sequence (Hanyu et al., 27 Jul 2025).

The conceptual distinction is therefore clear. Method A assumes a fixed order and equal budget partition. Method B uses a lightweight exploratory phase to estimate immediate impact and then imposes an order based on that estimate. The paper states that $\xi$0 controls the trade-off between ranking accuracy and budget for sequential optimization; the provided practical guideline gives $\xi$1 as an example (Hanyu et al., 27 Jul 2025).

A plausible implication is that Method B is intended to compensate for heterogeneity in parameter sensitivity without returning to fully joint high-dimensional optimization.

4. CIM-Tuner for SRAM-CIM accelerators

In the SRAM-CIM literature, CIM-Tuner is an automatic tool for hardware balancing and optimal mapping strategy under area constraint via hardware-mapping co-exploration (Chen et al., 26 Jan 2026). Its problem formulation is explicitly bi-level in the sense that it simultaneously considers hardware parameters and mapping strategy.

The hardware parameter set is

$\xi$2

where $\xi$3 is the grid of CIM macros, $\xi$4 is the Storage–Compute Ratio per macro, and $\xi$5 and $\xi$6 are the capacities of the on-chip input/output SRAMs (Chen et al., 26 Jan 2026). The mapping strategy is

$\xi$7

with each layer strategy $\xi$8 represented as the tuple

$\xi$9

Two optimization objectives are formulated. Throughput maximization is

$$\min_P TTS(P) \quad \text{subject to} \quad p_i \in [L_i, U_i], \; i=1,\ldots,5,$$0

subject to

$$\min_P TTS(P) \quad \text{subject to} \quad p_i \in [L_i, U_i], \; i=1,\ldots,5,$$1

$$\min_P TTS(P) \quad \text{subject to} \quad p_i \in [L_i, U_i], \; i=1,\ldots,5,$$2

and

$$\min_P TTS(P) \quad \text{subject to} \quad p_i \in [L_i, U_i], \; i=1,\ldots,5,$$3

Energy-efficiency maximization is

$$\min_P TTS(P) \quad \text{subject to} \quad p_i \in [L_i, U_i], \; i=1,\ldots,5,$$4

under the same constraints (Chen et al., 26 Jan 2026).

The framework attains generality through a matrix abstraction of a CIM macro. A macro is abstracted as a weight matrix of dimension $$\min_P TTS(P) \quad \text{subject to} \quad p_i \in [L_i, U_i], \; i=1,\ldots,5,$$5 stored in SRAM cells, an input vector of length $$\min_P TTS(P) \quad \text{subject to} \quad p_i \in [L_i, U_i], \; i=1,\ldots,5,$$6, a multiply-accumulate primitive producing a partial-sum vector of length $$\min_P TTS(P) \quad \text{subject to} \quad p_i \in [L_i, U_i], \; i=1,\ldots,5,$$7, and $$\min_P TTS(P) \quad \text{subject to} \quad p_i \in [L_i, U_i], \; i=1,\ldots,5,$$8 distinct bank-partitions each holding an $$\min_P TTS(P) \quad \text{subject to} \quad p_i \in [L_i, U_i], \; i=1,\ldots,5,$$9 block (Chen et al., 26 Jan 2026). Two derived parameters are

$$P^* = \arg \min_{P \in D_1 \times \cdots \times D_N} TTS(P).$$0

and

$$P^* = \arg \min_{P \in D_1 \times \cdots \times D_N} TTS(P).$$1

The compute latency per $$P^* = \arg \min_{P \in D_1 \times \cdots \times D_N} TTS(P).$$2-length input vector is

$$P^* = \arg \min_{P \in D_1 \times \cdots \times D_N} TTS(P).$$3

and the update latency for a full weight block is

$$P^* = \arg \min_{P \in D_1 \times \cdots \times D_N} TTS(P).$$4

(Chen et al., 26 Jan 2026).

At the accelerator level, all designs in the work follow a generalized three-stage template:

1. Input SRAM
2. CIM array
3. Output SRAM

Input activations are broadcast along macro columns, partial sums accumulate along macro rows, and off-chip DRAM communicates with Input SRAM and Output SRAM over a global bus of width $$P^* = \arg \min_{P \in D_1 \times \cdots \times D_N} TTS(P).$$5 (Chen et al., 26 Jan 2026).

The tool’s scope is therefore broader than layer mapping alone. It treats mapping as inseparable from the physical allocation of compute and storage resources.

5. Mapping strategy space and search procedure in SRAM-CIM

The SRAM-CIM version of CIM-Tuner uses a two-level mapping strategy.

At the accelerator level, the spatial scheduling choices are:

• Non-Reversed (NR, weight-stationary): CIM weights hold the layer’s weights; input SRAM holds activation tiles.
• Reversed (R, input-stationary): CIM weights are reprogrammed each tile; input activation is stored in CIM.

The temporal scheduling choices are:

• Input-Priority (IP): refill Input SRAM before re-programming CIM weights.
• Weight-Priority (WP): refill CIM weights first.

At the macro level, the tiling choices are:

• Accumulation-First (AF), with

$$P^* = \arg \min_{P \in D_1 \times \cdots \times D_N} TTS(P).$$6

bundling $$P^* = \arg \min_{P \in D_1 \times \cdots \times D_N} TTS(P).$$7 consecutive $$P^* = \arg \min_{P \in D_1 \times \cdots \times D_N} TTS(P).$$8-sized $$P^* = \arg \min_{P \in D_1 \times \cdots \times D_N} TTS(P).$$9-chunks for the same output channel.

• Parallel-First (PF), with

$$\beta_1,\beta_2 \in [0,2], \qquad \alpha,\gamma \in [0,2], \qquad \xi \in [0,0.3].$$0

bundling $$\beta_1,\beta_2 \in [0,2], \qquad \alpha,\gamma \in [0,2], \qquad \xi \in [0,0.3].$$1 consecutive $$\beta_1,\beta_2 \in [0,2], \qquad \alpha,\gamma \in [0,2], \qquad \xi \in [0,0.3].$$2-channels for the same input chunk.

For a matrix multiplication

$$\beta_1,\beta_2 \in [0,2], \qquad \alpha,\gamma \in [0,2], \qquad \xi \in [0,0.3].$$3

the numbers of macro-tiles are

$$\beta_1,\beta_2 \in [0,2], \qquad \alpha,\gamma \in [0,2], \qquad \xi \in [0,0.3].$$4

and the total macro invocations are $$\beta_1,\beta_2 \in [0,2], \qquad \alpha,\gamma \in [0,2], \qquad \xi \in [0,0.3].$$5 (Chen et al., 26 Jan 2026).

Because there are 2 spatial choices, 2 temporal choices, and 2 tiling choices, the overall mapping strategy space per layer consists of 8 choices (Chen et al., 26 Jan 2026).

The global search uses a two-stage simulated annealing over $$\beta_1,\beta_2 \in [0,2], \qquad \alpha,\gamma \in [0,2], \qquad \xi \in [0,0.3].$$6. The initialization sets $$\beta_1,\beta_2 \in [0,2], \qquad \alpha,\gamma \in [0,2], \qquad \xi \in [0,0.3].$$7 to the midpoint of the hardware search space, flattens all layers of equal $$\beta_1,\beta_2 \in [0,2], \qquad \alpha,\gamma \in [0,2], \qquad \xi \in [0,0.3].$$8 into groups, and uses a temperature schedule $$\beta_1,\beta_2 \in [0,2], \qquad \alpha,\gamma \in [0,2], \qquad \xi \in [0,0.3].$$9 with cooling rate $TTS(P) = \frac{\log(1 - 0.99)}{\log(1 - P_0(P))},$0 (Chen et al., 26 Jan 2026). Each iteration then:

1. Proposes $TTS(P) = \frac{\log(1 - 0.99)}{\log(1 - P_0(P))},$1 by randomly adjusting one of $TTS(P) = \frac{\log(1 - 0.99)}{\log(1 - P_0(P))},$2.
2. Prunes $TTS(P) = \frac{\log(1 - 0.99)}{\log(1 - P_0(P))},$3 if $TTS(P) = \frac{\log(1 - 0.99)}{\log(1 - P_0(P))},$4 or $TTS(P) = \frac{\log(1 - 0.99)}{\log(1 - P_0(P))},$5, among other constraints.
3. For each layer group, exhaustively tries its 8 mapping strategies and picks the best mapping by fast simulator.
4. Accepts $TTS(P) = \frac{\log(1 - 0.99)}{\log(1 - P_0(P))},$6 with Metropolis probability

$TTS(P) = \frac{\log(1 - 0.99)}{\log(1 - P_0(P))},$7

1. Updates the temperature by $TTS(P) = \frac{\log(1 - 0.99)}{\log(1 - P_0(P))},$8.

The search is accelerated by constraining buffer sizes and $TTS(P) = \frac{\log(1 - 0.99)}{\log(1 - P_0(P))},$9 to powers of two, dropping hardware candidates whose internal bandwidth falls below DRAM bandwidth, and grouping same-shaped layers to reduce repetitive mapping enumeration (Chen et al., 26 Jan 2026).

This design encodes a specific methodological commitment: hardware exploration is not separated from mapping exploration, but coupled to it by a fast simulation loop.

6. Empirical results, validation, and related directions

For the Coherent Ising Machine framework, evaluation was conducted on planted Wishart instances ($\beta_1$00) from the CIM-CACm benchmark, with the Ising Hamiltonian

$\beta_1$01

where $\beta_1$02 is drawn from the Wishart planted ensemble (Hanyu et al., 27 Jul 2025). Each hyperparameter configuration was tested over approximately 50 independent CIM-CACm runs to estimate $\beta_1$03, and all tuning experiments were executed on the Flow supercomputer at Nagoya University with Intel Xeon Gold 6230, 4 sockets×20 cores, 384 GiB DDR4, Python 3.7.6, Optuna 4.0.0, CACm 1.22 (Hanyu et al., 27 Jul 2025).

With a total budget of $\beta_1$04 trials, the paper reports:

• baseline with best-known $\beta_1$05, no retuning: TTS $\beta_1$06
• Method A with TPE: 1.47× speedup
• Method B with TPE: 1.65× speedup

Even under $\beta_1$07 trials, Method A reached up to 1.43× and Method B up to 1.46× improvements. The study further states that both methods lowered the mean TTS and reduced its variance, and that across all five optimizers in the portfolio, Method B consistently outperformed Method A and the conventional simultaneous-tuning baseline (Hanyu et al., 27 Jul 2025).

For the SRAM-CIM framework, the simulation setup was silicon-verified. The work used TSMC 28 nm, a behavioral Verilog implementation of the accelerator template, synthesis and PTPX for area and instruction-level power over a grid of hardware parameters, and a piecewise-linear fit within the simulator that yields <10% error vs. silicon-measured power. A taped-out test chip with 1×1 macro, SCR=16, IS=16 kB, OS=16 kB was used to verify instruction energy per macro operation (Chen et al., 26 Jan 2026).

Under a 5 mm² area budget, CIM-Tuner’s extended mapping strategy space, denoted ST, was compared with prior mapping using only spatial scheduling, denoted SO. Averaged over 7 networks, the reported gains were:

• 1.58× higher energy efficiency
• 2.11× higher throughput (Chen et al., 26 Jan 2026)

The paper also applies CIM-Tuner to published accelerators under their original area budgets. For TranCIM, the energy-efficiency optimum improved from 2.54 TOPS/W to 3.40 TOPS/W with ×1.34 improvement, and the throughput optimum reached 1028.9 GOPS with ×1.03 improvement. For TP-DCIM, the energy-efficiency optimum improved from 1.89 TOPS/W to 4.36 TOPS/W with ×2.31 improvement, and the throughput optimum reached 1326.7 GOPS with ×2.88 improvement (Chen et al., 26 Jan 2026). Runtime optimizations reduced co-exploration time by 80%, and hardware-space pruning removed 35% of candidates (Chen et al., 26 Jan 2026).

The papers also state their limitations explicitly. In the Coherent Ising Machine setting, the key assumptions include moderate interdependence among hyperparameters and the assumption that single-parameter optimization captures most of the variance in TTS; strong couplings may favor joint tuning (Hanyu et al., 27 Jul 2025). In the SRAM-CIM setting, the current work focuses on GEMM-style operators, with conv2D and reduction layers identified as possible extensions, and sparsity, mixed precision, and dynamic reconfiguration are not yet integrated (Chen et al., 26 Jan 2026).

A related direction is represented by CQ-CiM, which formulates a joint Compression-Quantization pipeline for hardware-aware embedding shaping in CiM-based retrieval. Its inclusion is mainly terminological: the work explicitly describes itself as acting as a universal “CiM-Tuner,” but the framework is published under a different title and addresses embedding adaptation rather than accelerator co-exploration or CACm hyperparameter tuning (Li et al., 23 Feb 2026).

Taken together, the literature uses CIM-Tuner to denote optimization frameworks that tune a parameterized search space around a CIM substrate, but the tuned object differs fundamentally across subfields: CACm hyperparameters in Coherent Ising Machines, and hardware-plus-mapping configurations in SRAM Computing-In-Memory accelerators.