Carry Gate: Quantum & Multi-Valued Logic

• Carry gate is a logic circuit that extracts, generates, or propagates the carry digit during addition, enabling the separation of sum and carry in both multi-valued and binary systems.
• They are implemented using ballistic transport in quantum point contacts and reversible logic circuits, achieving quantized conductance and optimized resource metrics like T-depth and CNOT-depth.
• Carry gates demonstrate strong scalability through cascading configurations and play a critical role in enhancing arithmetic efficiency in fault-tolerant quantum and multi-valued logic devices.

A carry gate is a logic circuit or quantum operation that extracts, generates, or propagates the “carry” digit or bit during arithmetic (typically addition). Carry gates are fundamental to the construction of both multi-valued (e.g., quaternary) and binary arithmetic devices, spanning classical, ballistic electronic, and quantum computing architectures. Their implementations embody essential trade-offs in reversibility, degree of parallelization, ancilla usage, and resource metrics such as cost and depth.

1. Ballistic Carry Gates for Multi-Valued Logic

Carry gates for multi-valued (quaternary or decimal) logic have been experimentally realized using ballistic transport in series-connected quantum point contacts (QPCs). In such a device, two QPCs (Q1 and Q2) are fabricated in a GaAs/AlGaAs heterostructure. Q2 is set to pass exactly four modes ($N_2=4$), while Q1 is modulated by the sum of two quaternary inputs $A$ and $B$, so that $N_1$ encodes $A+B\in \{0,\ldots,7\}$.

• For $N_1\le 4$, all charge carriers transmit through Q2 to drain D1, encoding the “sum” digit $S$.
• For $N_1>4$, only four modes pass to D1 (sum), and the excess $N_1-4$ are reflected or deflected into a secondary drain D2 (carry digit $C$).

The logic operation performed by the carry gate is: $$A+B = 4C + S,\qquad S=(A+B)\bmod 4,\quad C=\left\lfloor \dfrac{A+B}{4} \right\rfloor$$ Thus, the device automatically separates sum and carry digits via ballistic, mode-selective partitioning of electrons. Quantized conductance plateaus (at $G_{D1}=(2e^2/h)\min\{N_1,4\}$ and $G_{D2}=(N_1-4)\cdot 2e^2/h$ for $N_1>4$) permit direct, error-free readout. This architecture can be generalized for decimal logic, contingent on QPCs supporting ten well-resolved conductance modes (Seo et al., 2014).

2. Carry Gates in Reversible and Quantum Circuits

In reversible logic and quantum computation, carry gates generate the carry-out bit required for n-bit adders while preserving reversibility or unitarity. Their construction directly influences quantum cost, logical depth, and the overall performance of arithmetic circuits.

A prototypical example is the PPKN gate (“The PPKN Gate: An Optimal 1-Toffoli Input-Preserving Full Adder for Quantum Arithmetic”):

• The PPKN is a $4\times4$ reversible gate with inputs $(C_{\rm in},A,B,0)$ and outputs $(\mathrm{Sum},A,B,C_{\rm out})$.
• The mapping is:

$$C_{\rm out} = ab \oplus bc \oplus ca, \qquad \mathrm{Sum} = a\oplus b\oplus c$$

• It decomposes into one Toffoli gate and five CNOTs across four time-layers, yielding a quantum cost of 10 and a logical depth of 4, thereby reducing cost and depth compared to the standard HNG gate.

This gate naturally cascades to yield an $n$-bit ripple-carry adder by feeding $C_{\rm out}$ of one block to $C_{\rm in}$ of the next, achieving quantum cost $10n$ and depth $4n$ (Papakonstantinou, 12 Dec 2025).

3. Decomposition and Resource Metrics

Binary (qubit-based) carry gates can be implemented via standard universal gates within the Clifford+$T$ set. In the quantum ripple-carry adder of Cuccaro et al., the carry is realized by the “MAJ” (majority) gate, carrying out the transformation: $c_i = a_ib_i \oplus b_ic_{i-1} \oplus c_{i-1}a_i$ This is instantiated as a Peres gate acting on three wires $(a_i, b_i, c_{i-1})$. The Peres gate can be decomposed into:

• 5 CNOTs and 7 $T$ gates with $T$-depth 4 and CNOT-depth 5 using the optimized templates in Clifford+$T$ (Remaud, 2024).

Resource metrics relevant for fault-tolerant quantum computing are the $T$-cost, $T$-depth, CNOT-cost, and CNOT-depth. The cost and depth of the carry gate constrain the end-to-end performance, especially in surface-code-based quantum architectures where $T$-gates are significantly more expensive than CNOTs.

4. Circuit Optimizations and Trade-Offs

Ripple-carry adders are especially sensitive to the efficiency of carry gate construction. Naïvely, each bitwise carry (MAJ) and its uncomputation (UMA) would accumulate $T$-depths, but recent optimizations achieve greater efficiency:

• T-depth for each bit reduced from 6 (naïve) to 4 (optimized) by parallelizing $T$-layers, overlapping adjacent Toffoli/Peres gates, and cancelling $T$/$T^\dagger$ pairs across the V-shaped circuit structure.
• The Cuccaro carry’s optimized resource use per $n$-bit adder is $T$-depth $4n+O(1)$, CNOT-depth $8n+O(1)$, using only one ancilla.
• The Takahashi et al. (TTK) adder is ancilla-free, using only Toffolis and CNOTs, with $T$-depth $4n$ but doubled CNOT-depth versus Cuccaro.

A table summarizing these trade-offs:

Scheme	Ancillae	$T$-depth/bit	CNOT-depth/bit
Cuccaro	1	4	8
Takahashi	0	4	16

Fault-tolerant scaling affects which optimization is favored: if $T$-gates are significantly costlier than CNOTs, minimizing $T$-depth is prioritized (Remaud, 2024).

5. Scalability and Extended Functionality

Carry gates in both ballistic and quantum domains exhibit strong scalability and composability. For the ballistic, multivalued-logic regime, cascading Carry Gates enables arbitrary-length quaternary adders, with the output carry digit from one stage forming the bias input to the next. For decimal or higher-radix operations, implementation relies critically on achieving highly resolved, thermally stable conductance plateaus in QPCs.

In quantum logic, the modular design of PPKN and similar gates allows the direct construction of ripple-carry adders of arbitrary width. The overall circuit depth remains $O(n)$ due to the sequential nature of carry propagation, though partial parallelization is possible within cost constraints.

6. Experimental Performance and Physical Constraints

Ballistic carry gates fabricated on GaAs/AlGaAs achieve conductance quantization accurate to within 10%, error rates below $10^{-3}$ on second-long stability tests, and implied intrinsic temporal precision on the scale of 10 ps, supporting GHz-range operation. Performance is currently limited by external gate-voltage noise and the magnitude of subband spacings relative to thermal energy, with robust quantization demonstrated up to 30 K.

Room-temperature operation and decimal logic extension require further advances in subband energy engineering and disorder minimization, as larger subband spacing and finer control of conductance plateaus are essential (Seo et al., 2014).

7. Interpretive Context and Outlook

Carry gates function as a foundational abstraction bridging device physics and algorithmic architecture, with their implementations dictating the achievable efficiency of arithmetic at the hardware level. In the quantum setting, their decomposition into universal gates and careful balancing of resource metrics directly impacts scalability, error-correction overheads, and the practical feasibility of quantum arithmetic. In ballistic multi-valued logic, they demonstrate a minimal, compact embodiment of arithmetic separation, with the potential to generalize to higher-radix systems and operation at technologically relevant temperatures.

A plausible implication is that future advances in both subband engineering and quantum circuit optimization will further compress cost and depth, enhancing the centrality of the carry gate construction in classical, multi-valued, and quantum digital logic (Seo et al., 2014, Papakonstantinou, 12 Dec 2025, Remaud, 2024).