AutoAssert-1: Automated HDL Assertion Synthesis

• The paper introduces AutoAssert-1, which leverages LoRA fine-tuning with Unsloth to automate the generation of SystemVerilog assertions from HDL, achieving 97% accuracy on the VERT benchmark.
• The framework employs LoRA-based adaptation on LLaMA-3-7B, adapting both attention and feed-forward layers to balance performance and resource efficiency with roughly 0.52% trainable parameters.
• Evaluation on the VERT dataset shows significant improvements over traditional methods while acknowledging limitations like attribute-name inconsistency and dataset simplicity.

AutoAssert 1 is a framework for automated assertion generation from HDL and Verilog code that combines a LoRA fine-tuned LLM with the Unsloth training platform. It is presented as a resource-efficient approach to generating SystemVerilog Assertions for hardware verification, with the explicit aim of reducing the manual burden of writing assertions while avoiding the cost of full-model fine-tuning. In the reported best configuration, the system uses LLaMA-3-7B with LoRA rank $r=16$, $\alpha=16$, and all target layers enabled, reaching $97\%$ accuracy on the VERT benchmark (Zhong et al., 10 Aug 2025).

1. Problem Setting and Motivation

AutoAssert 1 is framed as a response to the increasing complexity of hardware systems and the corresponding difficulty of manual verification. The paper treats the target task as generating correct SystemVerilog assertions from Verilog or HDL source code, motivated by the observation that manual verification is time-consuming and error-prone, that state-space explosion makes exhaustive testing impractical, and that difficult verification settings may cover only $60\%-70\%$ of edge cases. The Intel Pentium FDIV bug is cited as an example of incomplete coverage causing major financial loss (Zhong et al., 10 Aug 2025).

The paper identifies three practical obstacles for prior machine-learning and large-language-model approaches. First, labeled HDL-to-assertion pairs are scarce because they require expert annotation. Second, general-purpose LLMs often do not model HDL syntax, temporal logic, or concurrency semantics adequately. Third, full fine-tuning of billion-parameter models is compute- and memory-intensive, making frequent retraining difficult. Within that framing, AutoAssert 1 is positioned not merely as an assertion generator, but as a low-cost domain-adaptation method intended to preserve the base model’s general knowledge while specializing it for hardware assertion synthesis (Zhong et al., 10 Aug 2025).

2. Core Architecture and Training Mechanism

The technical core of AutoAssert 1 is LoRA-based adaptation applied to a pretrained Transformer. For an original weight matrix $W \in \mathbb{R}^{d \times k}$, LoRA introduces low-rank matrices $A \in \mathbb{R}^{d \times r}$ and $B \in \mathbb{R}^{r \times k}$, with $r \ll \min(d,k)$, and models the update as $\Delta W = BA$, giving the adapted weight $W' = W + BA$. The original model weights remain frozen; only $\alpha=16$0 and $\alpha=16$1 are trained. The paper states that $\alpha=16$2 is randomly initialized with Gaussian noise scaled by $\alpha=16$3, while $\alpha=16$4 is zero-initialized so that $\alpha=16$5 at the start of training (Zhong et al., 10 Aug 2025).

LoRA is applied to both attention and feed-forward projections: q_proj, k_proj, v_proj, o_proj, gate_proj, up_proj, and down_proj. The paper interprets this as adapting both token interaction and nonlinear feature transformation. Unsloth serves as the efficiency layer for training, with three mechanisms highlighted: 4-bit quantization of base-model weights, reducing GPU memory usage by about $\alpha=16$6; fused kernel operations for faster computation; and gradient clipping plus layer normalization calibration to stabilize LoRA training and reduce overflow or explosion issues. The end-to-end workflow is described as: input Verilog or HDL code, feed it into a pretrained LLM, fine-tune with LoRA on HDL-to-assertion pairs, generate an SVA assertion, and validate the result with text metrics plus syntax and functional checks (Zhong et al., 10 Aug 2025).

3. Dataset, Models, and Experimental Configuration

The training and evaluation corpus is the VERT dataset from Menon et al., containing $\alpha=16$7 annotated pairs of Verilog or SystemVerilog code and assertions across $\alpha=16$8 categories derived from the Xiangshan processor. The split is $\alpha=16$9 training pairs, $97\%$0 validation pairs, and $97\%$1 test pairs. The assertions follow SVA syntax and cover cases ranging from basic logic constraints to timing requirements (Zhong et al., 10 Aug 2025).

The paper compares four open-source 7B models as base LLMs: Qwen-7B, DeepSeek-LLM-7B, Gemma-7B, and LLaMA-3-7B. It also reports results for GPT-4, Grok 3, Gemini 2.5 Flash, and Claude Sonnet 4 as closed-source comparators. Among the open-source models, LLaMA-3-7B is reported as the strongest starting point, which the authors attribute to its English-centric pretraining and stronger compatibility with HDL syntax. The training setup uses an NVIDIA 4090, learning rate $97\%$2, batch size $97\%$3, sequence length $97\%$4 tokens, and $97\%$5 training steps. For LoRA, rank values $97\%$6, $97\%$7, and $97\%$8 are tested; $97\%$9 values $60\%-70\%$0, $60\%-70\%$1, and $60\%-70\%$2 are tested; dropout is set to $60\%-70\%$3; and the best setting is reported as $60\%-70\%$4, $60\%-70\%$5, with all target layers enabled (Zhong et al., 10 Aug 2025).

4. Quantitative Results

The reported evaluation uses BLEU, ROUGE-1, ROUGE-2, ROUGE-L, and Accuracy. In the open-source base-model comparison, LLaMA-3-7B attains BLEU $60\%-70\%$6, ROUGE-1 $60\%-70\%$7, ROUGE-2 $60\%-70\%$8, ROUGE-L $60\%-70\%$9, and Accuracy $W \in \mathbb{R}^{d \times k}$0. The corresponding accuracies for Qwen-7B, DeepSeek-LLM-7B, and Gemma-7B are $W \in \mathbb{R}^{d \times k}$1, $W \in \mathbb{R}^{d \times k}$2, and $W \in \mathbb{R}^{d \times k}$3, respectively. Among the closed-source systems, the paper reports Accuracy values of $W \in \mathbb{R}^{d \times k}$4 for GPT-4, $W \in \mathbb{R}^{d \times k}$5 for Grok 3, $W \in \mathbb{R}^{d \times k}$6 for Gemini 2.5 Flash, and $W \in \mathbb{R}^{d \times k}$7 for Claude Sonnet 4 (Zhong et al., 10 Aug 2025).

The LoRA ablations are central to the paper’s empirical argument. For rank $W \in \mathbb{R}^{d \times k}$8, the model reaches Accuracy $W \in \mathbb{R}^{d \times k}$9; for $A \in \mathbb{R}^{d \times r}$0, Accuracy $A \in \mathbb{R}^{d \times r}$1; and for $A \in \mathbb{R}^{d \times r}$2, Accuracy $A \in \mathbb{R}^{d \times r}$3. The associated trainable-parameter counts and training times are $A \in \mathbb{R}^{d \times r}$4 million parameters and $A \in \mathbb{R}^{d \times r}$5 minutes for $A \in \mathbb{R}^{d \times r}$6, $A \in \mathbb{R}^{d \times r}$7 million parameters and $A \in \mathbb{R}^{d \times r}$8 minutes for $A \in \mathbb{R}^{d \times r}$9, and $B \in \mathbb{R}^{r \times k}$0 million parameters and $B \in \mathbb{R}^{r \times k}$1 minutes for $B \in \mathbb{R}^{r \times k}$2. On that basis, the paper identifies $B \in \mathbb{R}^{r \times k}$3 as the best tradeoff between performance and cost. The $B \in \mathbb{R}^{r \times k}$4 ablation yields Accuracy $B \in \mathbb{R}^{r \times k}$5 for $B \in \mathbb{R}^{r \times k}$6, $B \in \mathbb{R}^{r \times k}$7 for $B \in \mathbb{R}^{r \times k}$8, and $B \in \mathbb{R}^{r \times k}$9 for $r \ll \min(d,k)$0, again favoring the middle setting (Zhong et al., 10 Aug 2025).

A further ablation compares LoRA placement. With $r \ll \min(d,k)$1, adapting only attention layers yields Accuracy $r \ll \min(d,k)$2, adapting only feed-forward layers yields $r \ll \min(d,k)$3, and adapting all layers yields $r \ll \min(d,k)$4. The paper characterizes this as a $r \ll \min(d,k)$5 accuracy improvement over attention-only adaptation and a $r \ll \min(d,k)$6 improvement over feed-forward-only adaptation, with only a small increase in trainable parameters. The training-loss curve is described as dropping rapidly at the beginning and then stabilizing, and the optimal configuration is reported to achieve $r \ll \min(d,k)$7 functional accuracy on the test set (Zhong et al., 10 Aug 2025).

5. Limitations and Stated Constraints

The paper is explicit that its headline performance is partly shaped by benchmark characteristics rather than by unrestricted real-world generalization. One limitation is attribute-name inconsistency in generated assertions: the model may produce assertions whose functional content matches the reference while differing in the property name. Because of that, reported accuracy is computed only on the content after the property, rather than requiring full property-name consistency (Zhong et al., 10 Aug 2025).

A second limitation is the acknowledged simplicity of the dataset. The paper states that the high reported accuracy is partly due to the overly simplistic structure of the dataset and its limited task diversity. It also cautions that once tasks become more complex, such as broader hardware functions or multimodal inputs, LoRA alone is insufficient. The authors therefore identify several future directions: combining the approach with DPO for more stable preference optimization, possibly introducing AdapterFusion and few-shot learning, and adopting reward criteria such as grammatical validity, semantic correctness, and mutation coverage. These statements place AutoAssert 1 within a narrower design space than some later systems that emphasize realism, multimodal grounding, or formal bug-detection metrics (Zhong et al., 10 Aug 2025).

6. Position Within the Assertion-Generation Literature

AutoAssert 1 belongs to a broader line of work on automated assertion synthesis for hardware verification, but its emphasis is distinct. Whereas AutoAssert 1 focuses on parameter-efficient fine-tuning over HDL-to-assertion pairs, AssertCoder generates SVAs from multimodal specification documents and evaluates them with model checking and mutation testing, reporting average functional correctness of $r \ll \min(d,k)$8 and mutation detection rate of $r \ll \min(d,k)$9 across three RTL designs (Tian et al., 14 Jul 2025). AssertLLM2, by contrast, is a benchmark rather than a generator; it contains $\Delta W = BA$0 real-world designs across $\Delta W = BA$1 functional categories and argues that syntax and formal provability overestimate practical usefulness because mutation-based bug detection remains difficult even when syntax success is high (Wu et al., 26 May 2026).

A separate strand of work pushes assertion generation deeper into the module hierarchy. DeepAssert extracts module-level specifications from top-level specifications and RTL structure to generate deep assertions for internal modules (Wang et al., 18 Sep 2025). AssertMiner similarly uses AST-derived module call graphs, I/O tables, and dataflow graphs to ground module-level specification generation and assertion mining (Lyu et al., 13 Nov 2025). Repair-oriented systems extend the pipeline beyond generation: AssertFix is designed to locate and repair incorrect SystemVerilog Assertions, classifying failures into timing and logic errors and applying type-specific correction strategies (Lyu et al., 28 Sep 2025).

This suggests that AutoAssert 1 occupies a specific niche within the literature: it is less oriented toward multimodal specification understanding, formal coverage benchmarking, or post-generation repair than toward lightweight specialization of a pretrained LLM for HDL assertion synthesis. Its significance lies in showing that LoRA-based adaptation on a commodity setup can achieve high benchmark accuracy with about $\Delta W = BA$2 trainable parameters in the best configuration, thereby making assertion-generation experimentation and deployment more accessible under constrained compute budgets (Zhong et al., 10 Aug 2025).