Analog Multiplication & Addition

• Analog multiplication and addition are foundational operations that use device physics—such as charge conservation and transistor behavior—for efficient multiply-accumulate (MAC) functions.
• Various implementations, including switched-capacitor, subthreshold transconductor, pulse-domain integrate-and-fire converters, and memristor-based circuits, enable precise analog arithmetic.
• State-of-the-art designs achieve energy efficiencies of 2–10 fJ/MAC with high bandwidth, supporting scalable integration in deep learning accelerators and neuromorphic systems.

Analog multiplication and addition are foundational operations in signal processing, neural networks, and many real-time computation systems. In analog hardware implementations, multiplication and addition can be executed directly using native device physics—charge conservation, transistor transconductance, time-domain pulse arithmetic, or memristive resistance modulation—enabling high-throughput, low-energy computation at scale. Several distinct physical paradigms support analog multiply-and-accumulate (MAC) execution, spanning switched-capacitor circuits, subthreshold MOS transconductors, current-mode adders, pulse-domain signal algebra, and memristor-based networks.

1. Physical Implementations of Analog Multiplication and Addition

Analog MAC operations are realized through multiple circuit primitives, each leveraging different device mechanisms:

• Switched-Capacitor (SC) Multipliers: These circuits implement weighted multiplication by transferring charge between capacitors controlled by digital switches. Input voltages and quantized weights modulate the charge transfer, and summing occurs naturally on accumulation nodes. Performance metrics typically include 3–10 fJ/MAC energy, 200 MHz bandwidth, and 4–6 bit precision in 40 nm CMOS. Integration with non-volatile memory (e.g., RRAM, PCM) is achieved by programming the weighting element or associated reference voltages; 128×128 arrays are common organizational units (Liu et al., 2021).
• Subthreshold Transconductor Multipliers: Utilizing MOSFETs biased in the subthreshold regime, these topologies exploit the exponential current–voltage relation to implement analog multiplication. For inputs $V_X$ and $V_Y$, a “Gilbert-style” multiplier produces output currents proportional to the product or hyperbolic tangent of the gate voltages. Pipeline arrangements enable 128×128 MAC arrays, with energy/MAC near 5 fJ and 20 MHz bandwidth. Weighting can be modulated via memristive elements (Liu et al., 2021).
• Current-Mode Analog Adders: Summing is performed in current-domain circuits by connecting multiple output branches to a shared low-impedance node, buffered by a cascode or OTA. Summed currents integrate onto a feedback capacitance to provide the accumulated output, achieving > 200 MHz bandwidth and per-operation energies near 2 fJ (Liu et al., 2021).
• Pulse-Domain Calculation with Integrate-and-Fire Converters (IFC): Analog voltages x(t) are transformed into pulse trains where the pulse intervals encode signal amplitudes via time. In this domain, addition and multiplication are defined directly on the pulse sequences (+ₚ, ×ₚ), forming an exact algebraic field isomorphic to real numbers under addition and multiplication. Addition aligns pulse events such that cumulative intervals track amplitude sum, while multiplication constructs a new pulse sequence whose timing encodes the product of the input signals pointwise (Nallathambi et al., 2016).
• Memristor-Based Arithmetic Circuits: Memristors are used to store analog values as resistance states. Addition is accomplished through series connection (memristances sum), while multiplication is implemented in operational amplifier networks where the output voltage corresponds to the product of two programmed memristances. The system is programmed using feedback loops to set memristance values to match analog inputs, supporting addition, subtraction, multiplication, and division at the circuit level (Merrikh-Bayat et al., 2010).

2. Mathematical Principles and Device Equations

Each analog MAC technology is underpinned by specific device-level equations:

• Charge-Sharing Principle (SC Multipliers):

$$Q_{tot} = C_S V_{IN} + C_W V_W,\quad V_{OUT} = \frac{Q_{tot}}{C_S + C_W}$$

For constant or quantized weights, this achieves linear multiplication and is directly extendable to dot-product computation via charge accumulation.

• Subthreshold Operation (Transconductor Multipliers):

$$I_D = I_0 \exp\left(\frac{\kappa V_{GS} - V_{th}}{n V_T}\right)$$

This exponential dependence enables log-domain arithmetic, translating voltage sum to multiplication in the current domain.

• Current Summation (Adders):

$$I_{SUM} = \sum_{i=1}^N I_i, \quad C_F \frac{dV_{out}}{dt} = I_{SUM}$$

Analog addition is performed via Kirchhoff's law and charge integration.

• Pulse-Domain Field (IFC):
  • Addition: $P_z = P_x +ₚ P_y$ with timing $t^z_k = \inf\{t: N_x(t) + N_y(t) \geq k\}$.
  • Multiplication: Intervals combined according to a recursive law (see Eq. (2) in (Nallathambi et al., 2016)), matching real multiplication on reconstructed signals:

  $IFC^{-1}[P_x ×ₚ P_y](t) = x(t) \cdot y(t)$

• Memristor-Based Arithmetic:

$$M(q) = R_{\text{on}} \frac{w}{D} + R_{\text{off}}\left(1 - \frac{w}{D}\right)$$

$v_m(t) = M(q(t))\ i_m(t)$

Series connection realizes addition ($V_Y$0) and special op-amp networks implement multiplication ($V_Y$1 under the paper’s assumptions) (Merrikh-Bayat et al., 2010).

3. Algebraic Structures and Theoretical Properties

Multiple analog MAC approaches are shown to yield algebraic consistency with real arithmetic:

• IFC Pulse Fields: The operation sets $V_Y$2 (pulse addition) and $V_Y$3 (pulse multiplication) both form abelian groups. Distributivity of ×ₚ over +ₚ is proven, establishing a true field structure. Multiplicative and additive inverses are constructible, and mapping to and from the analog signal domain is injective (Nallathambi et al., 2016).
• Memristor Circuits: The natural arithmetic of resistance addition in series and the analog implementation of multiplication support field-like computation, limited by the physical precision and non-idealities of the devices (Merrikh-Bayat et al., 2010).
• Current and Charge Summation: In switched-capacitor and current-mode MACs, the accumulation process mirrors vector addition, and the property holds up to hardware limitations such as mismatch, noise, and area constraints (Liu et al., 2021).

4. Integration with Non-Volatile Memory and Large-Scale Architectures

Analog multiplication and addition circuits are tightly coupled with non-volatile memory systems for scalability:

• Crossbar Arrays: Dense RRAM or PCM crossbar arrays co-located with analog MAC tiles store weights as programmed conductance states, supporting in-memory multiplication and efficient analog vector-matrix products. Tiling strategies (e.g., 128×128 for SC cells, 64-deep pipelines for subthreshold multipliers) define accelerator scalability (Liu et al., 2021).
• Memristive Integration: Memristor-based arithmetic components are inherently nonvolatile and can be scaled to large arrays. Two-terminal topologies allow for high-density computation but require attention to array nonidealities such as sneak-path currents and device variability (Merrikh-Bayat et al., 2010).
• Pulse-Train Field Operations: The IFC pulse-field construction is asynchronous by design, offering intrinsic parallelism and supporting arbitrary precision in theory. In practice, timing control and device mismatch may limit large-scale integration (Nallathambi et al., 2016).

5. Representative Performance Metrics and Practical Constraints

The following performance characteristics are reported for state-of-the-art analog MAC implementations (Liu et al., 2021, Merrikh-Bayat et al., 2010):

Implementation	Energy/MAC	Bandwidth	Area/Cell	Precision
SC Multiplier	3–10 fJ	up to 200 MHz	~20 µm² (40 nm)	4–6 bits
Subthreshold Multiplier	~5 fJ	up to 20 MHz	~100 µm²	5–6 bits
Current-Mode Adder	~2 fJ/add	>200 MHz	~80 µm²	~5 bits
Memristor Arithmetic	Simulated	Not reported	Ultra-dense	~6–8 bits
IFC Pulse-Train Algebra	Asynchronous	Limited by firing	Not specified	Arbitrary (in theory)

System-level constraints include device variability, noise, temperature-induced drift, and the non-idealities associated with memristors and passive analog elements. For memristor circuits, programming precision is typically within ±1–2%, and analog computation accuracy is limited by noise floors and device repeatability. Scaling to large arrays requires mitigation of non-ideal switching paths and compatibility with CMOS integration (Merrikh-Bayat et al., 2010).

6. Applications, Opportunities, and Limitations

Analog multiplication and addition circuits are critical for deep learning accelerators, neuromorphic processing, and low-power edge devices:

• Deep Network Accelerators: Analog MAC blocks can serve as building units for edge and embedded deep neural networks, where energy efficiency and compact area are critical (Liu et al., 2021). Integration with softmax and exponential-normalization blocks allows for complete layer computations in analog hardware.
• Analog Algebraic Signal Processing: The IFC pulse-field construction reveals an alternative paradigm, in which all core arithmetic operations are performed via time-domain event manipulation, facilitating asynchronous, low-power, and potentially ultra-high-precision analog computation (Nallathambi et al., 2016).
• Emerging Non-Volatile Devices: Memristor-based arithmetic units provide compact, nearly passive implementations of basic operators, supporting future high-density mixed-signal computation; however, device non-idealities, drift, and integration limitations currently constrain their practical adoption (Merrikh-Bayat et al., 2010).

A plausible implication is that ongoing development of reliable, dense, and stable non-volatile memory elements—alongside CMOS-compatible analog circuitry—remains crucial to realizing the full potential of analog multiplication and addition in energy-efficient hardware acceleration.