Ambipolar Quantum-CMOS Platform

• Ambipolar Quantum-CMOS platforms are architectures that integrate both electron and hole quantum dots with conventional CMOS circuits for hybrid quantum logic.
• They leverage standard industry processes like FD-SOI and FinFETs to achieve tunable quantum dot formation, precise charge sensing, and effective spin control.
• These platforms promise scalable, wafer-scale integration with reconfigurable quantum and classical functionalities critical for next-generation quantum processors.

An ambipolar Quantum-CMOS platform refers to a complementary metal-oxide-semiconductor (CMOS) device architecture where both electron and hole quantum dots (QDs), as well as classical and quantum logic, can be defined, controlled, and sensed within the same material system and process flow. This capability is critical for developing scalable, hybrid qubit systems that integrate n-type (electron) and p-type (hole) qubits, associated charge sensors, and high-density control/readout circuitry on a single substrate. Ambipolarity is achieved using undoped or weakly doped channels, mid-gap contacts, or programmable doping methods, enabling reconfigurable quantum devices compatible with industrial CMOS fabrication standards. The platform facilitates seamless integration of quantum and classical circuits and leverages the unique properties of both charge carrier types in a silicon-based or emerging 2D materials context.

1. Device Architectures and Materials

Ambipolar Quantum-CMOS platforms are realized using several technological strategies:

• Planar Multilayer Pd-Gate MOS Architectures: Devices employ a multilayer palladium gate stack atop high-resistivity silicon with a 5.9 nm SiO₂ and 2 nm Al₂O₃ gate oxide. Three Pd gate layers define reservoir/barrier, inter-dot/screening, and plunger/sensor gates, allowing the formation of a hole double quantum dot (by negatively biasing plunger gates) and an adjacent n-MOS single-electron transistor (SET) for charge sensing. The two regions are laterally separated by ~100 nm, and both electron and hole QDs are fabricated on the same die without nonstandard doping (Jin et al., 2022).
• Industrial 22 nm FD-SOI Quantum Dot Arrays: In GlobalFoundries’ 22FDX™ platform, ambipolarity is achieved via an undoped silicon channel sandwiched between a 145 nm buried oxide (BOX) and a thin high-κ SiO₂ gate dielectric. Three or more polysilicon barrier gates locally control tunnel barriers and dot formation, while the back-gate bias determines electron (V_BG > +0.3 V) or hole (V_BG < –0.4 V) accumulation (Amitonov et al., 2024).
• FinFETs with Mid-gap Silicide Contacts: Ambipolarity in FinFETs is enabled using metallic NiSi source/drain contacts, whose Fermi level pins near the Si mid-gap (Φ_B ≈ 0.56 eV), removing the need for heavy n⁺ or p⁺ doping. Wrap-around TiN gates on undoped fins allow dual-mode field-effect (n- or p-type) as well as single-electron quantum dot operation (Kuhlmann et al., 2018).
• Silicon-on-Insulator Nanowires: Ambipolar SOI nanowires utilize standard poly-Si gate stacks wrapped around undoped channels with alternate n++ and p++ reservoirs. A single set of gates can accumulate either a 2DEG or 2DHG under appropriate bias (V_G>V_{e,th} or V_G<V_{h,th}) and define DQD configurations for both carrier types in situ (Duan et al., 2020).
• Rewritable 2D WSe₂ Quantum FETs: Electron-beam programmable doping in WSe₂/hBN FETs allows in situ, site-selective patterning of n- and p-type regions via trapped charges at the interface. Polarity can be reversibly switched without new masks or chemical processing, enabling rewritable and highly tunable ambipolar FET arrays (Lan et al., 6 Dec 2025).

2. Quantum Dot Definition and Ambipolar Control Mechanisms

Ambipolar operation is realized through different confinement and carrier injection schemes:

• Electrostatic Confinement: Gate-induced accumulation forms electron or hole quantum dots by locally depleting carriers (via barrier gates) while the back-gate or global bias determines carrier type. In FD-SOI and SOI nanowire platforms, tuning the back-gate or the main gate beyond specific threshold voltages switches the channel between n-type and p-type (e.g., V_BG > +0.3 V for electrons, V_BG < –0.4 V for holes) (Amitonov et al., 2024, Duan et al., 2020).
• Schottky-Barrier Engineering: FinFETs with NiSi mid-gap contacts exhibit ambipolarity as both electrons and holes can be injected into the channel under appropriate gate bias. The gate modulates the width and transparency of the Schottky barrier, supporting quantum dot formation for both carrier types (Kuhlmann et al., 2018).
• Programmable Doping: In WSe₂ FETs, a low-energy e-beam and applied set voltage V_SET modulate trapped charges at the dielectric interface, locally doping regions n- or p-type by tuning the Fermi level. Rewriting enables real-time reconfiguration of logic and quantum blocks (Lan et al., 6 Dec 2025).
• Gate Layouts and Coupling: Multi-gate stacks (e.g., three-layer Pd in (Jin et al., 2022)) and back-gate plus barrier gate configurations (e.g., QT0, QT1, QT2 in (Amitonov et al., 2024)) are used to define quantum dots, tune tunnel rates (t_c), and achieve fine control over singlet-triplet energies and charge occupancy.

3. Charge Sensing and Readout Techniques

Sensitive charge detection and high-fidelity readout of quantum dot states are core requirements:

• Proximal SET Charge Sensing: In (Jin et al., 2022), an n-MOS SET biased at the Coulomb peak flank detects changes in the local electrostatic potential due to hole occupancy changes in an adjacent DQD. The observed charge sensor current steps (ΔI_cs ≈ 5–10 pA) differentiate between distinct QD configurations (e.g., (1,1) vs. (2,0)), with linearized response ΔG(V_g) ≃ (dG/dV_g) ΔV_g.
• Reflectometry and SEB Charge Sensors: FD-SOI and SOI architectures employ radio-frequency reflectometry either directly at the gate or through integrated single-electron box (SEB) sensors. The SEB is capacitively coupled (C_c ≈ 0.1–0.2 aF) to its neighbor QDs, and charge transitions are detected via phase shifts Δφ ≈ –2Q_L(ΔC/C_par) at megahertz frequencies. Reported single-shot charge sensing bandwidth is up to Δf ≈ 1.64 MHz with SNR > 5:1, and minimum integration times of τ{min}^e = 160 μs (electrons) and τ{min}^h = 100 μs (holes) (Duan et al., 2020, Amitonov et al., 2024).
• Spin-to-Charge Conversion: Three-stage ELM (Empty–Load–Measure) pulse protocols enable singlet-triplet state discrimination via charge sensor readout, extracting, for example, hole singlet-triplet relaxation times T_{ST} = 11 ± 3 μs (Jin et al., 2022).
• Gate-Based Readout in 2D Materials: Scanning microwave impedance microscopy (sMIM) at 3 GHz in WSe₂ devices provides direct imaging of carrier type and enables monitoring of in situ reconfigurable logic blocks based on local doping (Lan et al., 6 Dec 2025).

4. Tunability and Control of Inter-dot Coupling and Spin States

Ambipolar Quantum-CMOS platforms exhibit precise tuning of quantum properties essential for scalable quantum information processing:

• Tunnel Coupling Control: Gate voltages modulate tunnel rates t_c (e.g., via Pd Jg electrodes or polysilicon barriers), enabling t_c values to be tuned over two decades (sub-μeV to tens of μeV): t_c ∝ exp(αV_{Jg}), with α ≈ 10–20 V⁻¹ (Jin et al., 2022). In FD-SOI, t_{12} is exponentially sensitive to the inter-dot barrier gate and can be adjusted from <1 μeV to >50 μeV (Amitonov et al., 2024).
• Spin Control: Hole spin states are addressed via electric dipole spin resonance (EDSR) using gate-driven microwave fields. The effective spin Hamiltonian includes SOI-mediated terms: H = gμBB·σ + H{EDSR}. Experimental demonstrations yield g-factor g ≈ 1.12 and linear resonances in spin-blockade readout. Spin-orbit coupling in holes allows all-electrical control; electron spins offer prolonged memory times (e.g., T_2 ≈ 28 ms in isotopically purified Si) (Jin et al., 2022, Duan et al., 2020).
• Device Performance Metrics: Key figures from reported architectures include: charging energies E_C of 3–17 meV, lever arms α ≈ 0.2–0.6, and operational temperatures from 10 mK up to 700 mK. Subthreshold swing S approaches the ultimate thermal limit (≈ 60 mV/dec) in optimized devices (Kuhlmann et al., 2018, Lan et al., 6 Dec 2025).

5. Logic Integration, Reconfigurability, and Scalability

Ambipolar Quantum-CMOS leverages both quantum and CMOS-classical logic integration:

• Monolithic CMOS Compatibility: All reported devices are fabricated with industry-standard CMOS process steps; architectures such as the 22 nm FD-SOI QDA (Amitonov et al., 2024) and SOI nanowires rely on standard poly-Si gates, silicide contacts, and do not require additional mask steps or doping beyond standard foundry flows. FinFET and planar Pd-gate devices likewise maintain compatibility with advanced CMOS logic routing (Jin et al., 2022, Kuhlmann et al., 2018).
• Scalable Integration: Device layouts support gate pitches of 50–100 nm, allowing dense quantum and classical sub-arrays. SEB and gate-based reflectometry sensors can be multiplexed for large-scale readout. The e-beam programmable doping approach enables rewritable logic, dynamic V_{TH} tuning, and “mask-free” patterning of quantum and control devices at the wafer scale (Lan et al., 6 Dec 2025).
• Logic Functionality and Rewriting: The ambipolarity allows for real-time reconfiguration between n-type and p-type conduction/fabrication of NOT and NOR/NAND gates on the same platform without physical rewiring, as demonstrated in electron-beam written WSe₂ FET arrays. CMOS inverter gains exceeding 70 have been reported, alongside sub-fJ switching energies (Lan et al., 6 Dec 2025, Kuhlmann et al., 2018).
• Hybrid Quantum Architectures: The platform enables mixed-mode quantum circuits: fast electron-based sensors/readout for hole-spin qubits, exchange-coupled electron and hole QD arrays, and co-fabrication of classical/quantum sub-circuits for robust on-chip control (Jin et al., 2022, Amitonov et al., 2024).

6. Performance Metrics and Comparison

A comparative summary of key device features is presented below:

Platform	Material/System	Tunnel Coupling (µeV)	Charge Sensitivity (µs)	Logic/Reconfig.	Integration Strategy
Pd-gate MOS DQD+SET	Si, multilayer Pd/Al₂O₃	<1 to tens	5–10 pA (dc)	Static	Planar, stacked gates (Jin et al., 2022)
FD-SOI 22FDX™ QDA+SEB	Si FD-SOI, poly-Si	<1 to >50	SNR>5:1 @100 Hz	Static	All gates CMOS-compatible (Amitonov et al., 2024)
FinFET mid-gap	Si, NiSi S/D, TiN gates	∼100 MHz–1 GHz	N/A	Switchable	Standard FinFET, mid-gap (Kuhlmann et al., 2018)
SOI nanowire	Si, dual poly-Si	Adjustable	100–160	Switchable	Standard SOI CMOS (Duan et al., 2020)
WSe₂ e-beam writable	2D WSe₂/hBN	E-beam-defined	N/A	Fully rewritable	Mask-free scanning (Lan et al., 6 Dec 2025)

All values as reported in the referenced studies. Device performance varies with tuning and fabrication.

7. Outlook and Prospects

Ambipolar Quantum-CMOS platforms are enabling pathways for large-scale, hybrid quantum processor architectures compatible with industrial CMOS technology:

• Million-qubit Arrays: The demonstration of quantum dot arrays, charge sensors, and cryo-compatible classical control circuitry within standard FD-SOI flows (22 nm) paves the way for ultra-dense, monolithic integration and industry-scale quantum devices (Amitonov et al., 2024).
• Quantum-Classical Co-integration: The co-fabrication of n-type sensors with p-type qubits, tunable tunnel couplings, and rewritable complementary logic supports a modular, scalable quantum-chip roadmap where reconfigurability, high fidelity, and classical control are co-optimized within the same physical architecture (Jin et al., 2022, Lan et al., 6 Dec 2025).
• Hybrid Electron-Hole Qubits: Combining millisecond electron-spin coherence with the strong spin-orbit coupling of hole systems may enable both memory and fast gate operations on a single platform (Duan et al., 2020).
• Wafer-scale and 2D Integration: The compatibility of e-beam programmable doping and site-selective ambipolarity with back-end-of-line CMOS processing offers unique prospects for wafer-scale, mask-free, rewritable quantum and classical logic arrays in atomically thin materials (Lan et al., 6 Dec 2025).

Each of these advances positions the ambipolar Quantum-CMOS platform as a cornerstone of scalable, heterogeneous quantum information hardware capable of leveraging both well-established silicon technology and new 2D material paradigms.