Silicon Hole Spin Qubits: Fast Electric Control

Updated 4 August 2025

Silicon hole spin qubits are quantum two-level systems that encode information in the spin states of holes, exploiting strong spin–orbit coupling for efficient electric control.
They are fabricated in CMOS-compatible architectures such as FinFETs and planar MOS dots, achieving Rabi frequencies over 600 MHz and single-qubit gate fidelities around 99.8%.
Scalable operation is enabled by tuning to sweet spots that suppress charge noise, thereby extending coherence times and allowing integration with classical electronics for quantum processing.

Silicon hole spin qubits are quantum two-level systems where quantum information is encoded in the spin states of individual holes confined in silicon nanostructures. Leveraging the interplay between strong spin–orbit coupling (SOI), tunable g-factors, and advanced industry-standard CMOS technology, these qubits promise ultrafast, all-electrical control, long coherence times, and scalability compatible with large-scale quantum architectures.

1. Fundamental Properties and Physical Basis

The underlying physics of silicon hole spin qubits arises from the strong spin–orbit interaction of valence band holes, a consequence of the p-type symmetry of the Bloch states. Unlike electron spins—which have weak SOI in silicon—holes couple their spin and orbital degrees of freedom, resulting in electric field-sensitive g-factors and enabling efficient electric dipole spin resonance (EDSR). In strongly confined geometries such as quantum dots or nanowires, heavy- and light-hole mixing further alters the effective g-tensor, typically yielding strong anisotropy and gate sensitivity (Voisin et al., 2015).

The effective Hamiltonian for a confined hole in the presence of a magnetic field $\mathbf{B}$ and gate voltage $V_g$ can be cast as

$\mathcal{H}(V_g) = \frac{1}{2} \mu_B \vec{\sigma} \cdot \hat{g}(V_g) \, \mathbf{B}\ ,$

where the real $3\times3$ $g$ -matrix $\hat{g}(V_g)$ reflects the local electrostatic environment and geometry-induced effects.

2. Device Architectures and Materials Platforms

Silicon hole spin qubits have been demonstrated in a range of CMOS-compatible architectures, including:

Nanowire and FinFET devices: Strong quantum confinement is realized by patterned fins or wires, typically formed with state-of-the-art SOI or FDSOI techniques. Gate electrodes electrostatically define (double) quantum dots capable of hosting one or a few holes (Voisin et al., 2015, Camenzind et al., 2021).
Planar MOS quantum dots: Overlapping gate stacks define dots in planar devices directly compatible with dense integration (Liles et al., 2018, Wang et al., 2023, Liles et al., 2023).
Ambipolar and multilayer gate structures: Combining n- and p-type structures for improved charge sensing and control (Jin et al., 2022).
Acceptor-based systems: Boron or other group III acceptors, especially near Si/SiO₂ interfaces, allow for harnessing the intrinsic spin–3/2 manifold for spin manipulation and coupling (Salfi et al., 2016).
Curved quantum wells: Strain- and geometry-engineered devices provide both large SOI and reduced charge noise over wide operating ranges (Bosco et al., 2022).

The compatibility of these approaches with industrial 300 mm CMOS fabrication processes enables reproducible, large-array deployment and monolithic integration with classical control electronics (Vorreiter et al., 1 Aug 2025).

3. Electrical Control and High-Speed Manipulation

A haLLMark of silicon hole spin qubits is their capacity for all-electrical, high-speed manipulation. Through SOI, AC voltages on gates modulate either the g-factor directly or the quantum dot potential, enabling transverse and longitudinal spin rotations.

g-Tensor Modulation Resonance (g-TMR): Rapid qubit control is achieved by modulating the g-tensor using gate voltages in the presence of a static magnetic field. The Rabi frequency is given by

$f_\text{Rabi} = \frac{\mu_B V_\text{ac}}{2h} \left[ \frac{1}{g_\parallel} \frac{\partial g_\parallel}{\partial V_g} \right] \frac{g_\parallel g_\perp B_\parallel B_\perp}{\sqrt{(g_\parallel B_\parallel)^2 + (g_\perp B_\perp)^2}} ,$

where $g_\parallel, g_\perp$ are g-tensor components along and perpendicular to the channel, and $B_\parallel, B_\perp$ are the magnetic field projections (Voisin et al., 2015).

Typical Performance: Reported Rabi frequencies exceed 600 MHz in realistic devices (Voisin et al., 2015, Froning et al., 2020), with recent fin field-effect transistors achieving up to 150 MHz above 4 K (Camenzind et al., 2021). Recent foundry-fabricated qubits achieve single-qubit gate fidelities of 99.8% and two-qubit gate quality factors of 240 (corresponding to a physical fidelity limit of 99.7%) (Vorreiter et al., 1 Aug 2025).
Isotropic and anisotropic control: SOI enables tuning between fast manipulation and long coherence times by gating the SOI strength ("spin–orbit switch"), providing highly flexible qubit operation (Froning et al., 2020).

4. Coherence and Charge Noise Suppression

While strong SOI is critical for fast gates, it enhances susceptibility to charge noise, which modulates the effective g-tensor and limits $T_2^*$ .

Sweet Spots and Sweetlines: By tuning gate voltages or orienting the applied magnetic field, specific operating points ("sweet spots") or lines ("sweetlines") are found where the first-order sensitivity of the Larmor frequency to electric field fluctuations is suppressed (Malkoc et al., 2022, Bassi et al., 17 Dec 2024). At these points, the longitudinal spin–electric susceptibility $\beta_\parallel = \partial f_L/\partial V$ vanishes, minimizing dephasing.
Performance Gains: At sweet spots (or sweetlines), dephasing times are boosted by orders of magnitude—up to the millisecond regime in simulations and reaching 88 $\mu$ s in natural silicon with experimental sweet spot operation (Piot et al., 2022).
Tunability: Sweetline locations can be shifted significantly by moderate gate voltage adjustments, allowing simultaneous alignment of multiple qubits for scalable, noise-robust architectures (Bassi et al., 17 Dec 2024, Wang et al., 2023).

5. Entanglement, Two-Qubit Gates, and Strong Spin–Photon Coupling

Mechanisms for entanglement and scalable architectures include:

Electrically Tunable Exchange: Two-qubit gates are realized by pulsing the exchange coupling between adjacent dots, modulating the Hamiltonian for conditional logic operations. Reported two-qubit gate fidelity limits are ~99.7% in natural silicon (Vorreiter et al., 1 Aug 2025).
Cavity Quantum Electrodynamics (cQED): Strong coupling between silicon hole spins and superconducting microwave resonators is achieved by SOI-enabled spin–charge hybridization, with spin–photon coupling rates as high as 330 MHz, large enough to exceed decoherence and cavity decay rates (cooperativity $C\sim1600$ ) (Yu et al., 2022). This enables fast, long-range interaction and quantum nondemolition readout.
Dipole-Dipole and Circuit QED: The spin–dependent dipole moments arising from SOI enhance long-range dipole–dipole coupling and make hole spins well suited for integration in modular quantum networks (Salfi et al., 2016).
Exchange-Only SOI Qubits: Three-hole-spin encodings exploit SOI for robust, all-electrical, low-leakage two-qubit gates via a single exchange pulse, without the requirement for rapid signal calibration or rotating frame operation (Bosco et al., 7 Oct 2024).

6. Device Engineering, Materials, and Scalability

Silicon hole spin qubits benefit from several scalable engineering features:

Large-Scale CMOS Integration: Devices developed on 22 nm and 300 mm foundry lines are compatible with monolithic integration of classical and quantum components (Bellentani et al., 2021, Vorreiter et al., 1 Aug 2025).
Operation at Elevated Temperature: Demonstrated operation above 4 K (with gate fidelities at or near the fault-tolerance threshold) relaxes cooling requirements and facilitates co-integration with control electronics (Camenzind et al., 2021).
Geometric and strain engineering: Optimizing cross-sectional aspect ratios, incorporating triangular channel geometries, and applying strain allows for tuning of SOI, g-factor anisotropy, and charge noise immunity (Bosco et al., 2020, Wang et al., 2023, Salfi et al., 2016).
Curved Quantum Well Designs: These architectures exploit geometry and strain to achieve high SOI and broad regions of charge noise immunity, enabling GHz-rate gates and strong photon coupling (Bosco et al., 2022).
Charge Sensing and Readout: Integration with ambipolar charge sensors (e.g., nMOS adjacent to p-type double dots) ensures reliable spin-to-charge conversion, enables direct measurement of singlet–triplet relaxation, and supports high-fidelity initialization and readout (Jin et al., 2022).

7. Outlook, Challenges, and Future Directions

Recent progress in high-fidelity silicon hole spin qubits puts them on par with, or in some metrics exceeding, electron spin qubits. Key opportunities and remaining challenges include:

Further suppression of nuclear hyperfine noise via isotopic purification; with $^{28}$ Si enrichment, $T_2$ times are expected to increase substantially (Vorreiter et al., 1 Aug 2025, Piot et al., 2022).
Scalable error correction is within reach due to gate fidelities exceeding the fault-tolerance threshold for both single- and two-qubit gates (Vorreiter et al., 1 Aug 2025).
Managing variability and disorder: While holes offer strong SOI and electric control, their increased sensitivity to disorder necessitates careful device optimization (Vorreiter et al., 1 Aug 2025, Bosco et al., 7 Oct 2024).
Architectural flexibility: Hybrid integration of electron and hole spin qubits on a shared silicon platform is feasible due to their similar device structures, opening new operational regimes for quantum–classical CMOs architectures (Vorreiter et al., 1 Aug 2025).
Novel control paradigms: Phase-driving approaches and Floquet-engineered robust gates are advancing control flexibility, addressability, and noise resilience (Bosco et al., 2023).

Silicon hole spin qubits, through their strong and tunable SOI, high-speed and all-electrical control, scalable fabrication, and demonstrated path toward noise-robust operation, represent a central technology for future scalable quantum processors.