Understanding 2.5D Chiplet Systems

• 2.5D chiplet systems integrate multiple pre-fabricated dies on an interposer, offering flexibility in performance, cost, and design for advanced computing needs.
• The architecture includes heterogeneous chiplets connected via dense metal traces on silicon or organic interposers, optimizing space and thermal management.
• Challenges involve designing effective partitioning methodologies and optimizing interconnects, with applications ranging from AI accelerators to scalable compute arrays.

A 2.5D chiplet system is an integrated platform in which multiple pre-fabricated dies ("chiplets") are mounted side by side on a silicon or organic interposer, interconnected using dense metal traces, through-silicon vias (TSVs), micro-bumps, or copper pillars. This hybrid integration enables system architects to partition complex functionality (e.g., CPUs, high-bandwidth memory, accelerators, I/O controllers) across independently sourced dies, which may be fabricated in disparate technology nodes and subsequently collocated in a single package. 2.5D integration bridges the gap between traditional 2D systems-on-chip (SoC) and vertically stacked (3D) ICs, offering flexible performance, cost, and design trade-offs suitable for advanced computing, AI, and high-performance systems.

1. Architecture, Taxonomy, and Integration Models

A 2.5D chiplet system consists of:

• Chiplets: Heterogeneous, independently designed dies (logic, memory, analog) at different technology nodes.
• Interposer: A substrate, typically silicon, glass, or organic, providing high-density wiring between chiplets via redistribution layers (RDLs), TSVs, or micro-vias, with or without on-interposer active logic.
• Bonding Technology: Micro-bumps (≤45 µm pitch) or copper hybrid bonds (≤0.25 µm pitch), enabling tight area and high inter-chip bandwidth.

Key integration categories (Chen et al., 2024):

• Passive Interposer: Purely routing/tracing, no active devices.
• Active Interposer: Embeds transistors or logic for signal boosting, monitoring, security, or even on-interposer NoC.
• Physical Variants:
  • Silicon bridges (short passive dies)
  • Package-on-package (PoP) stacking
  • Fan-out wafer-level packaging (FOWLP)
  • Heterogeneous chiplet layouts (rectangular or irregular)
  • 2.5D+3D hybrid stacking

The selection of interposer type and package style dictates cost, bandwidth, thermal, and mechanical properties.

2. Design Automation and Partitioning Methodologies

EDA flows for 2.5D systems require multi-layered optimization across partitioning, floorplanning, placement, and interposer routing (Chen et al., 2024, Graening et al., 26 Jul 2025, Iff et al., 3 Feb 2025, Wang et al., 21 Nov 2025, Parekh et al., 29 Apr 2025):

• Partitioning: Hypergraph- or GA-based approaches allocate SoC functional blocks to chiplets, balancing communication cost $C_{\rm comm} = \sum_{i,j} w_{ij} d_{ij}$, power, and yield (Chen et al., 2024, Graening et al., 26 Jul 2025). Technology node assignment algorithms (GA or simulated annealing) optimize for yield and NRE, exploiting heterogeneous process options (Graening et al., 26 Jul 2025).
• Placement & Floorplanning: Multi-objective optimization (wirelength, area, temperature, stress/warpage) is performed using sequence-pair, analytical, or ML-based placers. Surrogate-accelerated methods (e.g., RBFN-based thermal field prediction) enable agile exploration of large system spaces (Zhang et al., 4 Apr 2025, Wang et al., 21 Nov 2025, Parekh et al., 29 Apr 2025).
• Joint Placement–Topology Optimization: Frameworks such as PlaceIT and HexaMesh synthesize placement-dependent inter-chiplet topologies, adapt to link-length constraints, and directly minimize application latency for mixed traffic classes (Iff et al., 3 Feb 2025, Iff et al., 2022).
• EDA Integration: Full signoff extends to multi-physics (thermal, mechanical, electrical), DRC/ERC over interposer and TSV rulesets, and chiplet/protocol awareness (UCIe, BoW) (Chen et al., 2024).

Modern design flows embrace cross-domain ML surrogates (Chen et al., 2024, Zhang et al., 4 Apr 2025), physics-based compact models (Wang et al., 21 Nov 2025), and multi-fidelity simulators (Pfromm et al., 2024) for tractable yet accurate trade-off analysis.

3. Interconnect and Communication Protocols

Inter-chiplet interconnection—fundamental to 2.5D performance—incorporates silicon interposers, bridges, and/or photonic interposers, using advanced PHYs, topologies, and protocols:

• Link Types: Electrical (micro-bump, hybrid bond), optical (silicon photonics, microring resonators, PCMs) (Sunny et al., 2023, Taheri et al., 2022).
• PHYs: Miniaturized, low-parasitic, low-ESD I/O; direct signaling links ('DSL') replaced classical SerDes when packaging advances allow ultra-short, low-C_pkg and L_pkg connections (Haque et al., 13 Nov 2025).
• Protocols: UCIe, BoW, AIB standards, and custom lightweight PHYs for tailored bandwidth/latency/energy (Ottaviano et al., 2024).
• Network Topologies: Mesh, star, ring, placement-optimized graphs (PlaceIT, HexaMesh), congestion-aware, dynamically reconfigurable photonic interposers (Iff et al., 2022, Iff et al., 3 Feb 2025, Taheri et al., 2022).
• Deadlock/Fault Tolerance: NoC solutions (DeFT) guarantee deadlock-freedom and high reachability even in presence of vertical-link faults via virtual-network separation and congestion-aware adaptive VL selection (Taheri et al., 2021).

High-performance 2.5D interposers require careful electrical/optical co-design, crosstalk/IR-drop mitigation, and, for photonic interposers, dynamic gateway and wavelength allocation (Sunny et al., 2023, Taheri et al., 2022).

4. Thermal, Mechanical, and Reliability Considerations

Thermal path complexity and package-level mechanical reliability are dominant limiting factors in dense 2.5D systems (Zhu et al., 5 Dec 2025, Pfromm et al., 2024, Zhang et al., 4 Apr 2025, Wang et al., 21 Nov 2025, Parekh et al., 29 Apr 2025, Chen et al., 4 Aug 2025):

• Modeling Techniques: Innovations include multi-fidelity thermal models (FEM, RC, DSS) for agile and accurate prediction (Pfromm et al., 2024), high-performance layout-driven adaptive solvers (3D-ICE 4.0) for anisotropic and non-uniform structures (Zhu et al., 5 Dec 2025), and surrogate-accelerated frameworks for runtime DSE (Zhang et al., 4 Apr 2025).
• Placement-Aware Optimization: Co-optimization of wirelength, peak $T_{\rm max}$, and maximum stress/warpage using FE/compact models is critical for reliability (Parekh et al., 29 Apr 2025, Wang et al., 21 Nov 2025). Gradient-uniformity, rather than absolute $T$, strongly reduces mechanical failure risk.
• Thermal Bottlenecks: The interposer, molding, and TIM layers limit vertical and lateral heat spreading, often requiring fine-grained workload-aware power mapping. Non-uniform power distribution characteristics can dramatically alter PDN and TIM choices (Chen et al., 4 Aug 2025).
• Package Scaling Impact: Advanced packaging (hybrid bonding, µbump pitch < 0.5 µm) eliminates the need for classical on-die ESD structures and allows direct signaling, which unlocks chiplet miniaturization and composability (Haque et al., 13 Nov 2025).

Design flows increasingly couple thermal and mechanical constraints into system-level optimization, reflecting the observed magnitude of package-related failure modes.

5. Cost, Yield, and Economic Analysis

Cost-efficiency—central to 2.5D adoption—is governed by substrate/interposer type, partition granularity, technology node mix, and I/O overhead (Tang et al., 2022, Graening et al., 26 Jul 2025, Chen et al., 2024):

• Cost Models: Analytical and empirical models aggregate die/interposer/test/assembly costs, bonding yield, package NRE/RE, and the effects of heterogenous process assignment ($C_\mathrm{total}$) (Tang et al., 2022, Graening et al., 26 Jul 2025).
• Partitioning Trade-offs: Finer chiplet granularity improves yield but increases assembly/pin/bonding costs. Optimal balance arises from system scale, node costs, and I/O driver limitations (Tang et al., 2022, Graening et al., 26 Jul 2025).
• Heterogeneous Integration: Mixed-node partitioning (e.g., logic at 7 nm, I/O/memory at 12–16 nm) yields up to 43% cost reduction vs. homogeneous strategies, especially when system area exceeds the 2D reticle limit (Graening et al., 26 Jul 2025, Tang et al., 2022).
• Interposer Impact: Organic interposers are cost-effective for modest bandwidth and area (<200 mm²), while silicon interposers pay off only for stringent bandwidth or area scaling (Tang et al., 2022).
• I/O and Packaging: Packaging scaling with hybrid bonding and direct signaling reduces I/O area overhead, enabling further cost and form-factor gains (Haque et al., 13 Nov 2025).

Cost-aware partitioning and floorplanning methodologies, such as ChipletPart, integrate technology assignment and physical feasibility for practical, manufacturable 2.5D designs (Graening et al., 26 Jul 2025).

6. Application Domains and Case Studies

2.5D chiplet systems have been demonstrated across diverse domains:

• AI/ML Acceleration: Integration of RISC-V clusters, photonics, HBM2E, and custom MAC arrays for high-throughput, energy-efficient ML inference (Occamy, (Paulin et al., 2024); silicon photonic interposers, (Sunny et al., 2023, Taheri et al., 2022)).
• Control Systems: Real-time, low-overhead RISC-V controllers (ControlPULPlet) leverage energy-efficient D2D protocols compatible with SoC and SiP contexts (Ottaviano et al., 2024).
• Security: Active-interposer architectures enabling system-level root-of-trust, physical separation, and runtime monitoring for secure integration of untrusted chiplets (Nabeel et al., 2020).
• Scalable Compute Arrays: Networks with hundreds of chiplets using topologies such as HexaMesh provide reduced diameter and increased bisection bandwidth, improving latency and throughput (Iff et al., 2022).
• LLM-Driven Optimization: LLM-based multi-agent frameworks (CHICO-Agent) optimize cross-layer architectural parameter sets, providing reproducible low-cost and Pareto-optimized design points (Wu et al., 20 Apr 2026).

These case studies confirm that 2.5D integration flexibly accommodates performance, cost, and reliability targets across a range of next-generation large-scale computing applications.

7. Challenges, Best Practices, and Future Directions

Key challenges span EDA limitations, design closure, interface standardization, and co-optimization of electrical, thermal, and mechanical domains (Chen et al., 2024, Wang et al., 21 Nov 2025):

• Unified multi-physics co-design flows, integrating ML-augmented surrogate models, are required for scalable DSE and signoff (Chen et al., 2024, Pfromm et al., 2024, Wang et al., 21 Nov 2025).
• Standardization (UCIe, BoW), open-source controller primitives (Ottaviano et al., 2024), and plug-and-play physical IP are critical for ecosystem scaling.
• Fine-grained, workload-aware physical and thermal modeling, coupled with advanced package-level cooling/interposer technologies, will be necessary as power densities and chiplet counts increase (Chen et al., 4 Aug 2025, Zhu et al., 5 Dec 2025).
• Active-interposer designs (with embedded NoC/security/control) and package-embedded photonic networks represent promising extensions for throughput, reliability, and security (Taheri et al., 2022, Sunny et al., 2023, Nabeel et al., 2020).
• Assembly/testing innovations, such as dielet-level test insertion, boundary-scan for chiplets, and holistic chip-package co-verification, remain open research fronts (Chen et al., 2024).

2.5D chiplet systems have matured into a mainstream design paradigm capable of addressing post-Moore scaling, system reuse, heterogeneity, and rapid time-to-market, provided ongoing advances in cross-domain EDA and package-aware design methodologies (Chen et al., 2024, Graening et al., 26 Jul 2025, Haque et al., 13 Nov 2025).