SpikON: A Dual-Parallel and Efficient Accelerator for Online Spiking Neural Networks Learning

Abstract: Spiking neural networks (SNNs) have emerged as a promising paradigm for energy-efficient brain-inspired computing. However, existing online unsupervised SNN learning suffers from low training accuracy and poor scalability. Although current online supervised learning algorithms perform well on large-scale datasets and networks, the non-hardware-friendly operations hinder efficient edge deployment. In this work, we propose SpikON, the first algorithm-hardware co-design framework for efficient and scalable end-to-end online supervised SNN learning. We first propose the learnable threshold through time and scaled weight centralization through time techniques to address the inefficiency of traditional algorithms. Moreover, to reduce latency and energy consumption, we introduce the novel training dataflow and cascade computation reuse scheme for SNNs that allows concurrent forward-backward computation and temporal reuse across timesteps. We further design the dedicated SNN accelerator with a dual-parallel engine and customized SIMD-based SNN core for efficient end-to-end online learning. Experiments show that the SpikON algorithm achieves 32.2% and 35.0% reductions in training latency and energy consumption over the baseline, without sacrificing accuracy. Moreover, the SpikON co-design achieves 7.2x (11.5x) and 26.8x (15.8x) training throughput (energy efficiency) compared with the edge Apple M4 GPU and TPU-like accelerator, respectively. The code is available at https://github.com/peilin-chen/SpikON.

• The paper introduces hardware-friendly normalization alternatives (LTTT and sWCTT) that reduce latency and energy overhead in online SNN training.
• It employs a dual-parallel design with bi-directional temporal parallel dataflow (BTP) and CTCR to accelerate training throughput.
• Empirical results demonstrate up to 26.8x throughput improvements and 42.7x energy efficiency gains over conventional methods.

SpikON: A Dual-Parallel and Efficient Accelerator for Online Spiking Neural Networks Learning

Introduction and Motivation

Spiking Neural Networks (SNNs) provide a compelling brain-inspired architecture for energy-efficient computation, leveraging event-driven binary spike communication and inherent sparsity. Despite recent progress in supervised online SNN learning through gradient-based methods, practical deployment on edge hardware is hindered by non-hardware-friendly normalization schemes, computational inefficiency across multiple timesteps, and lack of dedicated, scalable training accelerators. Prior approaches employing Batch Normalization (BN) or scaled Weight Standardization (sWS) for online learning become a bottleneck, especially with streaming, batch-size-one learning scenarios on edge devices.

SpikON introduces an algorithm-hardware co-design targeting efficient and scalable end-to-end online supervised SNN training. The central contributions include (1) learnable threshold through time (LTTT) and scaled weight centralization through time (sWCTT)—two normalization-substituting innovations minimizing overhead and hardware complexity; (2) a novel bi-directional temporal parallel (BTP) training dataflow and cascade temporal computation reuse (CTCR) strategy, both significantly reducing training latency and energy; and (3) a dedicated SIMD-based dual-parallel SNN accelerator implementing these algorithmic innovations.

Algorithmic Innovations

Learnable Threshold Through Time (LTTT) and Scaled Weight Centralization Through Time (sWCTT)

Conventional normalization techniques like BN and sWS are ill-suited for single-sample, streaming SNN training and induce both latency and energy overhead. SpikON replaces these with hardware-friendly, temporally adaptive mechanisms:

• LTTT introduces timestep-specific, learnable firing thresholds for each LIF neuron in the network, dynamically modulating spike rates and membrane potential distribution without requiring costly normalization operations. This temporal adaptation aligns with the online learning regime and introduces negligible parameter overhead.

  Figure 2: Overview of the LTTT (timestep-wise dynamic thresholds) and sWCTT methods integrated at the neuron and weight level, respectively.

• sWCTT centralizes weights (zero-centering) and applies a learnable, timestep-specific scaling factor to the weights at each layer, stabilizing weight distributions through temporal adaptation while further avoiding variance computation inherent to sWS.

The forward and backward passes are thus free from normalization-related bottlenecks while maintaining competitive convergence and representational dynamics.

Online Supervised SNN Algorithm Reformulation

Compared to backpropagation through time (BPTT), online SNN learning removes temporal error propagation, allowing instant, timestep-local gradient updates. This hybridizes the learning pipeline, decoupling gradient computation from temporal dependencies and enabling greater hardware parallelization.

Figure 3: Comparison of the classic BPTT versus online SNN learning, highlighting the elimination of temporal backpropagation and enabling timestep-wise gradient updates.

Bi-directional Temporal Parallel (BTP) Dataflow

Conventional sequential processing of each timestep, both in forward and backward passes, underutilizes available hardware parallelism. The proposed BTP dataflow interleaves forward passes of adjacent timesteps and parallelizes backward passes across timesteps, massively improving throughput.

Figure 1: (a) Bi-directional temporal parallel training dataflow and CTCR scheme: forward passes interleaved across timesteps; backward passes fully parallelized. (b) Microarchitecture of a BTP-dataflow lane.

Cascade Temporal Computation Reuse (CTCR)

SNNs processing static or slowly varying inputs exhibit high spatial spike similarity across adjacent timesteps. CTCR exploits this by caching and reusing computation results between adjacent timesteps, only recalculating sparse differences. Theoretical analysis and empirical results on CIFAR-100 and DVS-CIFAR10 confirm that this strategy significantly amplifies sparsity and accelerates training.

Figure 6: Cosine similarity between spike outputs of adjacent timesteps in VGG11 SNNs, demonstrating exploitable temporal redundancy.

Figure 4: CTCR method consistently improves layer-wise sparsity between timesteps, as exemplified on CIFAR-100 and DVS-CIFAR10.

Hardware Co-Design

SpikON Accelerator Architecture

At the hardware level, SpikON realizes a dual-parallel engine design built around 24 BTP-dataflow lanes, each supporting sparse/dense computation, with dedicated local SRAMs enabling computation reuse for CTCR. A customized SIMD-based SNN core executes neuron-specific and general arithmetic efficiently, while global controllers orchestrate high-level coordination.

Figure 5: Overall SpikON accelerator architecture with global/instruction SRAMs, BTPE, SIMD SNN core, and memory hierarchy.

Figure 9: Area and power breakdown: BTP engine and SNN core dominate total usage, aligning with the parallelization and memory reuse focus.

A lean custom ISA and five-stage pipeline ensure the SNN core remains an efficient, non-blocking complement to the parallel temporal lanes.

Throughput and Energy Evaluation

SpikON hardware achieves substantial improvements compared to state-of-the-art edge (Apple M4) and server (Nvidia A40) GPUs and a TPU-like training accelerator. The co-design demonstrates 32.2% latency and 35.0% energy reduction over prior algorithmic baselines and boosts both throughput and energy efficiency by an order of magnitude over leading hardware competitors.

Figure 7: SpikON significantly outperforms edge/server GPU and ASIC baselines in normalized training throughput and energy efficiency on both static and neuromorphic datasets.

Ablation experiments solidify the impact of individual contributions: BTP alone enables a 3.8x throughput speedup, while CTCR and sparsity-aware processing units collectively deliver up to 71% energy reduction in forward computations.

Figure 8: Ablation of BTP, sparsity-aware PU, and CTCR: each incrementally boosts throughput and/or reduces energy consumption.

Empirical Results

Benchmarks on CIFAR-10, CIFAR-100, DVS-CIFAR10, and DVS128-Gesture show that SpikON with LTTT+sWCTT matches or exceeds the accuracy of sWS-based online SNN learning, while reducing per-epoch training time and energy by over 30%. Throughput gains reach up to 26.8x over TPU-like hardware, and energy efficiency improvements peak at 42.7x over the Nvidia A40 server GPU.

Figure 10: Baseline comparison confirms high overhead for BN and sWS in single-sample online training, motivating SpikON's innovations.

Qualitative analysis confirms CTCR's greater benefits for static datasets (higher temporal spike similarity), while event-based neuromorphic datasets see moderate but consistent efficiency improvements.

Implications and Future Directions

The SpikON co-design framework demonstrates that algorithm-hardware synergy, when tailored to the temporal and sparsity structure of SNNs, enables scalable, efficient supervised online learning on resource-constrained hardware. The replacement of normalization layers with learnable temporal adaptation mechanisms (LTTT and sWCTT) both preserves accuracy and drastically reduces hardware complexity. The proposed parallel temporal execution and computation reuse strategies serve as templates for future SNN accelerator designs.

Potential extensions include support for recurrent SNN architectures, scaling to larger and more diverse spatiotemporal tasks, and integration with ultra-low-power neuromorphic substrates. The framework also practically advances the deployment of real-time adaptive SNN models in edge and IoT devices, making online supervised learning feasible at scale.

Conclusion

SpikON establishes the first algorithm-hardware co-design for efficient and scalable online supervised SNN training, eliminating the bottlenecks of legacy normalization and enabling parallel, energy-conscious operation. Its combination of temporal parameter adaptation, parallel dataflow, and fine-grained computation reuse sets a new technical baseline for practical, high-performance SNN acceleration.