A High-Precision Frequency Locking Method Based on All-Phase FFT Demonstrated on a Crystal Oscillator with Rubidium Clock Reference

Abstract: This article proposes a novel frequency-locking method based on frequency-domain unbiased phase estimation (FDUPE) for high-precision frequency control. By performing weighted recombination of the acquired data followed by Fourier-transform processing, the phase at the center of the data segment can be estimated without bias, making the method suitable for frequency-locking applications. The principle of the proposed method is analyzed, and an electronic prototype is developed to experimentally validate its feasibility. In the prototype, analog-to-digital converters (ADCs) are used for signal digitization, and a field-programmable gate array (FPGA) is used to implement the FDUPE algorithm. A digital proportional-integral-derivative (PID) controller is also implemented on the FPGA to provide feedback for accurate frequency locking. In the experiment, a (10~\mathrm{MHz}) voltage-controlled oscillator (VCO) with a free-running Allan deviation of (1 \times 10^{-9}) at (1~\mathrm{s}) is used as the device under test (DUT), while a rubidium atomic clock with an Allan deviation of (2 \times 10^{-11}) at (1~\mathrm{s}) serves as the high-stability reference source. Experimental results show that the proposed system achieves excellent locking performance, reducing the standard deviation of frequency fluctuations from (12.75~\mathrm{mHz}) root-mean-square (rms) in the free-running state to (0.88~μ\mathrm{Hz}) rms after locking. Correspondingly, the Allan deviation at (10~\mathrm{s}) is reduced from (9.6 \times 10^{-10}) to (1.45 \times 10^{-14}), representing a five-order-of-magnitude improvement in frequency stability.

• The paper presents an APFFT-based frequency locking technique that provides unbiased phase estimates and reduces measurement noise to 2.3 µHz rms.
• The methodology employs dual-channel high-resolution ADCs and FPGA implementation, achieving over five orders of magnitude improvement in frequency stability.
• Experimental results validated the approach by locking a 10 MHz VCO to a rubidium clock, reducing RMS deviation from 12.75 mHz to 0.88 µHz.

High-Precision Frequency Locking via All-Phase FFT: Methods, Analysis, and Experimental Demonstration

Introduction

Contemporary frequency-critical systems in metrology, timing, and communications require high-stability oscillators with robust frequency locking against environmental fluctuations. Digital frequency locking based on time-domain processing, while attractive for its compactness and integration, is fundamentally constrained by phase and noise estimation accuracy. This paper introduces a frequency-locking technique leveraging All-Phase Fast Fourier Transform (APFFT) for unbiased, high-resolution phase estimation directly in the frequency domain, demonstrated on a crystal voltage-controlled oscillator (VCO) phase-locked to a rubidium clock reference (2606.17959). Relative to conventional approaches such as digital quadrature demodulation (DQD), numerically controlled oscillator (NCO)-based architectures, or classic FFT approaches, the method aims for order-of-magnitude improvements in frequency stability while retaining moderate implementation complexity suitable for FPGA platforms.

Methodology and Theoretical Analysis

The APFFT-based locking scheme employs simultaneous, dual-channel digitization of the reference (REF) and device-under-test (DUT) signals via high-resolution ADCs. Preprocessing reorganizes the data to suppress endpoint-induced phase bias endemic to conventional FFT processors, using a triangular-weighted, overlap-add strategy to form a center-aligned sub-sequence for Fourier analysis.

Analytically, the APFFT’s core advantage lies in its ability to produce unbiased center-sample phase estimates irrespective of signal frequency-bin alignment. The variance of the phase estimation error is derived and shown to scale optimally with sample number, SNR, and bin offset, substantially outperforming raw FFT-based estimators which suffer additional bias and spectral leakage. The resulting closed-loop feedback derives instantaneous frequency deviation from phase differences across sequential APFFT windows, feeding a digital PID controller implemented on FPGA to actuate the control voltage for the VCO.

Error and Noise Analysis

A comprehensive stochastic analysis addresses three fundamental contributors to frequency measurement error: system thermal noise, ADC quantization noise, and sampling clock jitter. Analytical expressions are derived for each error’s contribution to frequency deviation estimation. Notably, under high-SNR and high-ENOB (effective number-of-bits) regimes, the thermal and quantization errors can be managed to sub-microhertz levels, while clock jitter is rendered negligible using a state-of-the-art jitter cleaner generating sub-100 fs rms clock signals.

Parameter sweeps using Monte Carlo simulation confirm that for realistic hardware (ENOB ≈ 12, SNR > 70 dB, $N=2048$), system measurement floors below $2.3~\mu$Hz are achievable. Importantly, a tradeoff exists in selecting the APFFT segment length ($N$); while longer windows improve noise suppression, they also increase hardware latency and may not proportionally improve resolution if bin offset grows.

FPGA Implementation and Hardware Validation

The APFFT-based system is realized on a Xilinx XC7K325TFFG900-2 FPGA, enabling real-time parallel processing of REF and DUT streams at 100 MSps. The architecture maintains moderate resource utilization (LUT: 19.5%, BRAM: 22.9%, DSP: 8.3%) and sub-100 $\mu$s pipeline latency.

Noise floor tests using a split rubidium source confirm measurement noise at $2.3~\mu$Hz rms, closely matching the theoretical floor. Locking experiments discipline a 10 MHz VCO (free-running Allan deviation $1 \times 10^{-9}$ at 1 s) to a SAFRAN LPFRS-01 rubidium atomic clock. The feedback loop stabilizes the VCO frequency deviation from $12.75$ mHz rms (free-running) to $0.88~\mu$Hz rms (locked), with Allan deviation at 10 s falling from $9.6 \times 10^{-10}$ to $1.45 \times 10^{-14}$—an improvement exceeding five orders of magnitude.

Comparative Assessment

In direct comparison with the dual-mixer time difference method (ADC-based-DMTD), the APFFT-based method achieves superior locking performance, reducing locked state frequency deviation (rms) by $2.3~\mu$0 and Allan deviation at 10 s by more than $2.3~\mu$1. This substantial reduction in residual feedback noise is directly attributable to the APFFT’s ability to extract unbiased phase information and more effectively suppress spectral leakage and phase distortion from finite windowing, which fundamentally limit classic DMTD and FFT approaches.

Implications and Future Directions

The proposed APFFT-based frequency locking method offers significant practical advantages for integrated, high-precision frequency control in compact hardware platforms. The frequency measurement noise achieved is competitive with or superior to the Allan deviation of advanced reference sources, meaning the technique does not substantially degrade system-level stability. The fully digital, FPGA-friendly implementation demarcates a path toward miniaturized frequency standards, on-board satellite/space platforms, high-precision frequency comb stabilization, and other low-SWaP (size, weight, and power) applications where robust long-term frequency control is paramount.

Theoretically, the demonstrated strong agreement between analytical error modeling, simulation, and experimental results validates the underlying stochastic model for APFFT frequency-domain estimators, and suggests that further architectural enhancements—such as expanded window length, adaptive SNR weighting, or real-time compensation for non-idealities—could yield even better performance as ADC and FPGA technology progresses.

Conclusion

This work systematically establishes the APFFT-based digital frequency-locking methodology as a technically sound, high-precision solution to the oscillator disciplining problem. By leveraging frequency-domain preprocessing and unbiased phase estimation, it surpasses prior approaches both in numerical locking performance and noise resilience, with experimental validation on FPGA hardware. It is poised to impact instrumentation, timing, and quantum technology applications requiring extreme frequency stability under practical hardware and environmental constraints.