LLM-Driven Design Space Exploration of FPGA-based Accelerators

Abstract: Designing field-programmable gate array (FPGA)-based accelerators for modern artificial intelligence workloads requires navigating a large and complex hardware design space encompassing architectural parameters, dataflow strategies, and memory hierarchies, making the process time-consuming and resource-intensive. While the SECDA methodology enables rapid hardware-software co-design of accelerators through SystemC simulation and FPGA execution, identifying optimal accelerator configurations still requires substantial manual effort and domain expertise. This work presents SECDA-DSE, a framework that integrates LLMs into the SECDA ecosystem, comprising tools built around SECDA to automate the design space exploration (DSE) of FPGA-based accelerators. SECDA-DSE combines a structured DSE Explorer for generating accelerator configurations with an LLM Stack that performs reasoning-guided exploration using retrieval-augmented generation and chain-of-thought prompting, alongside a feedback loop that enables reinforced fine-tuning for continuous improvement. We demonstrate the feasibility of SECDA-DSE through an initial high-level synthesis based evaluation of a generated accelerator design that meets synthesis timing and resource constraints on an Zynq-7000 FPGA.

• The paper presents an automated SECDA-DSE framework that leverages LLMs to generate and refine FPGA accelerator designs efficiently.
• The framework integrates a DSE Explorer with an LLM Stack to iteratively optimize designs using metrics like latency and resource consumption.
• Experimental results show design feasibility with a 3.95 ns critical path and minimal resource usage on a Zynq-7000 platform.

LLM-Driven Design Space Exploration of FPGA-based Accelerators: An Expert Overview

Introduction

The complexity of architecting efficient FPGA-based accelerators for AI workloads is compounded by large multidimensional design spaces and intricate hardware-software co-design requirements. Traditional approaches, even when leveraging SystemC-enabled flows such as SECDA, are limited in scalability and efficiency due to their reliance on manual tuning and domain-expert iteration. The SECDA-DSE framework directly addresses these limitations by introducing automated, LLM-driven design space exploration (DSE) tightly integrated with the SECDA ecosystem, enabling both the generation and iterative refinement of accelerator designs. This essay provides an in-depth analysis of the proposed framework, its methodological innovations, experimental validation, and the broader implications for DSE automation in accelerator design.

SECDA-DSE Framework Architecture

SECDA-DSE is architected around two principal components: the DSE Explorer and the LLM Stack, orchestrated in a cyclic workflow that iteratively refines hardware accelerator designs.

Figure 1: SECDA-DSE framework architecture, highlighting the interaction of the DSE Explorer with the LLM Stack.

The DSE Explorer acts as a generator of candidate configurations, leveraging domain constraints and template-driven instantiation of SECDA-compliant architectures. It explores permutations defined by the target AI workload, FPGA platform, and explicit architectural directives, generating run artifacts (e.g., SystemC source, HLS-generated RTL, bitstreams) and evaluating them via simulation and synthesis.

Concurrently, the LLM Stack serves as the intelligent reasoning agent. It consumes hardware datapoints, context extracted by RAG from the SECDA-TFLite codebase, and outputs from prior exploration. The LLM Stack guides design iteration by ranking, refining, and filtering configurations based on both direct evaluation feedback and chain-of-thought (CoT) prompted stepwise reasoning.

The interaction between the two cores is mediated by a cost model database populated with metrics such as latency, resource consumption, and simulation outcomes, enabling reinforced evolution over exploration rounds rather than static one-shot generation.

DSE Explorer: Automated Structured Parameter Generation

The DSE Explorer's operation is centered on structured, template-driven parameter space traversal.

Figure 2: Workflow of the DSE Explorer, comprising configuration generation, simulation evaluation, and results collation.

Inputs include the targeted DNN or AI kernel class, the FPGA device type, and a set of architectural directives constraining the search space (e.g., tiling factors, compute array widths, buffer sizing). From these, it produces SECDA-native templates for hardware instantiation, mapping each permutation to a discrete evaluation instance.

Outputs from simulation and HLS synthesis are aggregated, with metrics distilled to concise "hardware datapoints" (design files, resource/latency statistics). These form the input substrate for further refinement by the LLM Stack, establishing a data-driven exploration-evaluation feedback loop.

LLM Stack: Retrieval-Augmented, Reasoning-Driven Design Refinement

The LLM Stack is modular, comprising RAG and evaluation modules, with extensible integration via model-agnostic APIs.

Figure 3: LLM Stack Architecture—the coordination of RAG, fine-tuning modules, and evaluation context with external SECDA interfaces.

• Retrieval-Augmented Generation (RAG): Uses vectorized indices over commented SECDA-TFLite codebase and performance logs to provide model context for each iteration. Crucially, only contextually relevant snippets (e.g., interface specifications, previous configurations with similar characteristics) are fed into the LLM, maintaining prompt efficiency without truncating design-relevant data.
• CoT Prompting: The stack enforces structured, step-by-step reasoning, facilitating decomposition of complex design criteria and explicit trade-off analysis, especially during architectural branching (e.g., parallelism vs. resource budgeting).

  Figure 4: Chain-of-Thought (CoT) prompting pipeline for enhancing LLM-guided hardware design reasoning.

• Parameter-efficient Fine-tuning (LoRA): The LLM Stack adapts incrementally to the SECDA problem domain via LoRA-based fine-tuning on accumulated exploration data, allowing specialization without catastrophic forgetting or full-model retraining.

Evaluation remains semi-automated within the presented scope, with initial human-in-the-loop feedback to filter unviable architectures and annotate negative datapoints, but this is designed to be phased out as hardware data representation grows.

Experimental Validation

Initial results validate the loop by specifying, in natural language, the structure of an element-wise vector multiplication accelerator. The LLM Stack generated a fully SECDA-compatible SystemC implementation, meeting timing (3.950 ns critical path vs. 5.00 ns target at 200 MHz) and resource constraints (e.g., minimal % utilization of BRAM, LUTs, and DSPs).

Key numerical outcomes for the generated design (target: Zynq-7000 xc7z020):

• Latency range (across modules): 0–2060 cycles (0–10.3 µs).
• Resource utilization: 2% BRAM18K, 1% DSP48E, <2% LUT/FF used.
• The pipeline was not fully instantiated at the top level (II = latency), but all functionality was correct-by-construction via HLS.

SECDA-DSE thus demonstrates end-to-end translation from high-level user intent to deployable hardware templates, with the LLM actively shaping feasible, toolchain-compliant implementations.

Implications and Future Perspectives

The integration of LLMs into DSE for FPGA-based accelerators represents a technical inflection point with several immediate and longer-term implications:

• Practical Automation: By systematizing exploration and using LLM reasoning to guide parameter refinement, domain experts are unburdened from exhaustive manual iteration, with the framework adapting to the hardware co-design context over time.
• Template-Guided Constrained Generation: Unlike prior works that target unconstrained generative approaches, SECDA-DSE harnesses domain templates and device-specific ranges to exclude semantically invalid or resource-violating configurations, increasing iteration efficiency and result reliability.
• Feedback-Driven Adaptation: The accumulation of hardware datapoints, including both positive and negative (invalid) configurations, enables continual model specialization via LoRA, supporting transferability across new workloads, devices, and potentially, non-FPGA architectures.
• Scalability Challenges: Full automation at large design-space scale remains computationally intense, even with simulation-based rapid evaluation; exploration efficiency and selection coverage will require further augmentation through optimal search and pruning strategies.
• Evolution Towards Autonomy: The framework is positioned for a human-out-of-the-loop operational mode contingent on collecting sufficiently diverse and representative hardware log datasets.

Conclusion

SECDA-DSE establishes a systematic, LLM-driven workflow for the design space exploration of FPGA-based AI accelerators, unifying structured parameter generation, reasoning-guided refinement, and simulation-validated evaluation within the SECDA environment. Preliminary results confirm the viability of translating user-level intent into functionally correct accelerator designs under hardware constraints. Future work will involve scaling the architecture and benchmark sets, full MCP-driven subcomponent automation, comparative evaluation across LLM variants, and large-scale SECDA-native accelerator database expansion, further delineating the boundary between LLM-driven automation and domain-expert design paradigms.