Akita: A High Usability Simulation Framework for Computer Architecture

Abstract: Computer architecture simulation is essential for evaluating new designs without the need for costly tapeout. The community has developed dozens of valuable simulators that have enabled significant architectural advances. However, using and developing simulators remains a major barrier due to ad-hoc component interfaces, strict deployment requirements, the burden of managing performance optimizations like parallelization at the component level, and limited monitoring and visualization capabilities. The root cause of these limitations is the systematic neglect of user and developer experience in favor of technical functionality. We believe that only by separating technical concerns from user and developer experience concerns -- through a dedicated simulation engine decoupled from hardware models -- can the community overcome these fundamental obstacles and enable more productive architectural research. Akita embodies this philosophy as a dedicated simulation engine that cleanly separates infrastructure from architectural models. Smart Ticking and Availability Backpropagation let developers write simple cycle-based code while achieving event-driven performance. Parallel simulation happens transparently -- developers write single-threaded code while Akita handles multi-core execution. Akita's simple, uniform, yet powerful simulation tracing support enables real-time monitoring and post-simulation visualization. We demonstrate the flexibility of Akita through case studies, including the development of a trace-based DNN simulation and a RISC-V CPU simulation, showing how prioritizing developer experience accelerates architectural research.

• The paper presents Akita's engine-centric design that decouples model logic from scheduling via Smart Ticking, achieving a 2.68× speedup.
• It employs transparent PDES to handle parallel simulation, automating thread safety and synchronization for enhanced scalability.
• Akita integrates robust tracing, monitoring, and visualization tools that improve debugging, accelerate research cycles, and ensure composability.

Akita: Architecture-Agnostic Simulation Engine for High Usability

Introduction

The paper "Akita: A High Usability Simulation Framework for Computer Architecture" (2604.28073) presents Akita, a simulation engine designed to decouple simulation infrastructure from architectural model implementations, thereby directly targeting usability bottlenecks endemic to extant computer architecture simulators. The architecture simulation ecosystem suffers from monolithic systems with tightly coupled models, ad-hoc interfaces, and significant developer overhead, especially regarding parallelization, monitoring, and trace instrumentation. Akita's engine-centric approach addresses these issues through explicit separation of concerns, transparent optimization strategies, and comprehensive tracing and visualization support.

Engine-Level Design and Separation of Concerns

Akita embodies modular simulation infrastructure, abstracting and centralizing core functionalities including time advancement (cycle-based and event-driven), inter-component communication, metrics collection, tracing, monitoring, and visualization. The engine-centric philosophy enables:

• Developers to focus solely on hardware model logic, unconcerned with lower-level event scheduling or performance optimization.
• Reuse and composability: researchers can integrate models from diverse sources with protocol-first interfaces enforced at the engine.
• Uniform instrumentation: tracing and monitoring are available via a universal API, separate from component logic.

This separation is not merely structural; it systematically reduces repeated optimizations, facilitates community-driven component sharing, and accelerates research cycles. Akita leverages the Go programming language, delivering static binaries with cross-platform deployment, obviating the dependency hell and toolchain mismatches seen in C++-based frameworks.

Smart Ticking and Availability Backpropagation

Akita achieves event-driven performance without sacrificing the developer-favored cycle-based interface by introducing Smart Ticking. Components declare simple Tick methods, the engine autonomously schedules events only when actual progress can be made based on buffer availability and component state. Availability Backpropagation generalizes this by propagating buffer state backward through ports and connections, ensuring necessary wake-ups to eliminate futile polling.

Smart Ticking yields an average simulation speedup of 2.68× over baseline cycle-based execution, as shown in the experimental evaluation.

Figure 1: Smart Ticking speeds up simulations by 2.68X on average.

The numerical results validate that idle-tick elimination, coupled with conservative scheduling, maintains simulation accuracy (error <1%) while addressing core simulation scalabilities.

Transparent Parallel Simulation

Parallel simulation is transparently handled via conservative Parallel Discrete Event Simulation (PDES). Developers write only single-threaded component code, and the engine manages event partitioning, synchronization, and locking. This approach obviates explicit management of thread safety and event ordering at the component level, demonstrating a performance speedup between 1.88× and 2.38× for up to 16 cores. Notably, limitations in parallelism (e.g., sequential workloads) are automatically addressed via Smart Ticking, further optimizing per-core utilization.

Tracing, Monitoring, and Visualization

Akita introduces aspect-oriented task-based tracing, recording hierarchical relationships and contextual information for each event/task (e.g., instruction, memory transaction). The tracing APIs—StartTask, EndTask, TagTask—minimally intrude on component logic and are deployable across all model types. Enhanced debugging capabilities exploit the task tree structure to provide architecture-aware backtraces, directly linking bugs and performance anomalies to originating architectural events.

The integration with Daisen delivers post-simulation visualization, with cycle-by-cycle and aggregated performance analytics. The interface permits inspection of component execution timelines, hierarchical task relationships, and per-component metrics without any simulator code modification.

Figure 2: Daisen visualization integrated with Akita, showing (A) an overview of metrics, (B) hierarchical tasks, (C) execution timelines, and (D) task legend.

Real-time monitoring via AkitaRTM enables live debugging, hang detection, bottleneck analysis, and interactive profiling. The performance analysis framework stores all trace and metric data in robust, queryable databases (SQLite, MySQL, MongoDB, CSV), supporting advanced post-processing and bottleneck identification.

Evaluation and Numerical Results

Technical evaluation leverages the MGPUSim multi-GPU simulator with Akita's features toggled, running a suite of diverse benchmarks. Smart Ticking improves execution time by 2.68× on average with <1% error, and parallel simulation adds another 1.88×–2.38× speedup depending on core count. Task-based metric tracing incurs a 20% slowdown, considered acceptable for the rich data collected.

Case studies include:

• Onira: A 5-stage in-order RISC-V timing simulator, developed in weeks by a novice, achieves 10–20% CPI error compared to RTL for microbenchmarks, preserving memory-level parallelism (MLP) and pipeline scaling behaviors.

Figure 3: MLP trend comparison.

• TrioSim: A trace-driven event-level DNN workload simulator for multi-GPU systems, validating high-level execution models against physical multi-GPU PyTorch setups.

User Experience and Developer Productivity

An IRB-approved survey of active Akita users (16 participants) reflects strong positive sentiment for software architecture coherence, code quality, cross-platform deployment, and usability. Documentation needs improvement, and users desire richer performance metric support and low-level hardware behavior introspection. Developer automation (Smart Ticking, parallel simulation, debugging) and first-party components receive consistently high ratings.

Figure 4: To what degree do you agree with the statements?

Practical and Theoretical Implications

Akita's engine-centric paradigm, combined with transparent optimization and instrumented analysis, establishes a new benchmark for usability in architecture simulation. Practically, it accelerates model development and reduces debugging and experiment iteration time. Theoretically, it lays groundwork for community-wide infrastructure: composable architectures, systematic simulation methodologies, and tooling standardization.

Akita's architecture enables rapid prototyping, modular integration, and robust introspection—features well aligned with trends in architectural exploration, heterogeneous computing, and scalable hardware simulation. As AI hardware development continues to escalate, frameworks like Akita will be instrumental in supporting complex design-space exploration, validating execution models, and integrating domain-specific accelerators.

Conclusion

Akita represents a rigorously engineered simulation infrastructure designed to decouple technical implementation from usability demands. With Smart Ticking, transparent parallelization, comprehensive tracing, and integrated visualization, it achieves significant improvements in simulation speed, developer efficiency, and experiment insight. The engine-centric model sets a foundation for community-oriented simulation frameworks supporting rapid architectural innovation, composability, and robust analysis—key requirements as the complexity and scale of computer architectures and AI workloads continue to evolve.