Converting an Integer to a Decimal String in Under Two Nanoseconds

Abstract: Converting binary integers to variable-length decimal strings is a fundamental operation in computing. Conventional fast approaches rely on recursive division and small lookup tables. We propose a SIMD-based algorithm that leverages integer multiply-add instructions available on recent AMD and Intel processors. Our method eliminates lookup tables entirely and computes multiple quotients and remainders in parallel. Additionally, we introduce a dual-variant design with dynamic selection that adapts to input characteristics: a branch-heavy variant optimized for homogeneous digit-length distributions and a branch-light variant for heterogeneous datasets. Our single-core algorithm consistently outperforms all competing methods across the full range of integer sizes, running 1.4-2x faster than the closest competitor and 2-4x faster than the C++ standard library function std::to_chars across tested workloads.

• The paper presents a fully SIMD-based conversion method using AVX-512 IFMA and precomputed reciprocals to extract decimal digits without costly division.
• It employs dual-variant strategies and precomputed constants to optimize arithmetic operations, reducing instruction counts and cycle overhead by up to 72%.
• Empirical evaluations show 1.4 GB/s throughput on eight-digit inputs, outperforming state-of-the-art scalar approaches in both performance and efficiency.

SIMD-Accelerated Integer-to-Decimal Conversion: An Authoritative Analysis

Problem Formulation and Prior Work

The conversion of binary integers to variable-length decimal strings is omnipresent in systems-level and application-level code—spanning logging frameworks, database serialization, file I/O, and data interchange formats like JSON and CSV. Despite its ubiquity and its direct impact on end-to-end system throughput, this operation has received limited formal algorithmic innovation, with most contemporary strategies grounded in classic recursive division, small-digit lookup tables, or hybrid variants.

Existing high-performance methods often trade off between arithmetic reductions (minimizing costly division/mod operations via two-digit, four-digit, or five-digit block decompositions and fixed-point reciprocal multiplication), table-driven approaches optimized for cache locality or code simplicity, and scalar implementations aiming for branchless codepaths. While SIMD (Single Instruction, Multiple Data) capabilities have been leveraged to accelerate similar serialization bottlenecks (e.g., base64 and UTF-8 transcoding [clausecker2023transcoding], [mula2020base64]), integer-to-string conversion, especially for 64-bit wide values and variable-length outputs, has remained dominated by scalar techniques.

Algorithmic Contributions and AVX-512IFMA Leveraging

This paper introduces a fully SIMD-based integer-to-string conversion algorithm that exploits AVX-512 IFMA instructions. The approach is grounded on the theoretical foundation that multiplicative inverses, rather than divisions, suffice to extract decimal digits when constants are precisely chosen and precomputed. The method is dual-path: it features a branch-heavy variant for homogeneous digit-length distributions, and a branch-light variant for mixed-length datasets, selecting the optimal method dynamically based on sampled input statistics.

The conversion pipeline consists of:

• Chunking: Each input (up to 20 digits) is split into 8- or 16-digit blocks using reciprocal multiplication for the initial division by $10^8$ or $10^{16}$.
• Parallel Remainder Extraction: Using VPMADD52LUQ/HUQ, multiple digit positions are extracted in parallel across the 512-bit AVX-512 lanes (eight 64-bit words), applying precomputed reciprocal constants to avoid division.
• ASCII Packing and Storing: Efficient AVX-512 permute and mask-store instructions assemble the converted digits and store only the required number of bytes, supporting both variable- and fixed-length storage depending on the selected variant.

The arithmetic is validated by an explicit bound on the required precomputed constants (Theorem 1), ensuring correctness for all 64-bit unsigned inputs up to $10^{16}$.

SIMD Kernel and Implementation Details

The AVX-512 SIMD kernel enables the computation of all needed decimal remainders for an 8- or 16-digit block in parallel. The structure avoids all division instructions, instead relying on:

• Precomputed Constants: For each digit position $k$, use constants $c_k = \lfloor 2^{52} / 10^k \rfloor$, enabling the extraction of each digit via multiplicative-hardware instructions.
• VPMADD52LUQ/HUQ: Perform multiply-add in 52-bit lanes, suitable for the decimal base, producing both quotient and remainder with a concise operation sequence—requiring only five assembly instructions per 8-digit block.

For mixed-length input, masked stores apply; for batches with uniform digit lengths, direct aligned stores achieve optimal throughput.

Adaptive Dual-Variant Strategy

A lightweight dynamic selection mechanism samples input to estimate the digit-length distribution. If the data is homogeneous (single digit-length dominant), the branch-heavy (homogeneous) algorithm is selected; otherwise, the branch-light variant is used. This sampling incurs negligible overhead (below 0.1% of total conversion time for even small batches), and the design is validated to be robust across compilers and dataset characteristics.

Empirical Performance Evaluation

The algorithm's efficacy is rigorously benchmarked on AMD Zen 5 processors with AVX-512, using both real-world and synthetic datasets that span variable and fixed digit-length distributions. Against highly optimized competitors—Google's Abseil, jeaiii, yy_itoa, AppNexus, and baseline std::to_chars—the AVX-512 algorithm demonstrates superior absolute and relative performance in all but the shortest digit cases:

• Throughput: Achieves 1.4 GB/s on eight-digit homogeneous datasets, 2–4× faster than std::to_chars, and up to 2× faster than the top scalar competitors.
• Scalability: On 1–8 digit variable-length workloads, maintains a 33% improvement over the fastest scalar strategy.
• Instruction Count: Homogeneous variant executes ~10–12% fewer instructions per digit, yielding up to 72% fewer cycles per conversion, conditional on branch predictability.

  Figure 2: Performance comparison (ns/n, lower is better) of top algorithms on three real-world datasets, showing AVX-512's consistent advantage and up to 1.4 GB/s throughput.

• Dominance for Larger Digit-Lengths: For digit counts greater than three, the AVX-512 kernel dominates, with a particularly notable advantage for common database/timestamp-sized integers (7–10 digits).

  Figure 4: Performance across all digit lengths (1–20) on homogeneous datasets of 1M integers each; AVX-512 method outperforms from 3 digits onward.

Implications and Future Directions

The results decisively demonstrate that SIMD parallelism, specifically with fused multiply-add integer instructions, enables new complexity and efficiency frontiers in a long-stagnant systems subroutine. For real-world applications—ranging from columnar database engines to JSON serialization and high-frequency logging—this translates directly to increased aggregate throughput and reduced latency for data serialization workloads.

Future areas for research and development include:

• Portability to Other Architectures: Direct extension to ARM SVE/SVE2 or RISC-V V could generalize SIMD acceleration of conversion on non-x86_64 platforms, though with nontrivial adaptation given differences in fused multiply-add semantics.
• Batch Modes and Groupwise Vectorization: Investigating strategies where multiple integers are processed simultaneously within AVX-512 lanes, further amortizing setup costs and potentially unlocking additional instruction-level parallelism.
• Integration with Floating-Point Formatting: As floating-point to decimal also relies on a final integer-to-string rendering (at smaller digit counts), these approaches could be applied to the last stage of Ryū/Dragonbox-style routines.
• Broader SIMD-Layered Serialization: Applying similar principles to other text encoding, parsing, and conversion bottlenecks within binary-to-textual conversion pipelines.

Conclusion

This paper presents a formally justified and empirically superior SIMD-based integer-to-decimal string conversion algorithm leveraging AVX-512 IFMA. The dual-variant dynamic architecture achieves both theoretical optimality in arithmetic operations and empirical dominance in all practical workload regimes for 64-bit integer serialization. With negligible adaptivity overhead, this work represents a substantial advancement in both algorithmic and systems implementation for high-performance string formatting (2604.26019).