Architecture-aware Unitary Synthesis

Abstract: We present a novel architecture-aware transpilation method for exact general unitary gate synthesis on superconducting quantum hardware. Our approach is tightly integrated with the optimized block-ZXZ decomposition, exploiting its recursive structure to make hardware-aware decisions at each level of the recursion rather than treating transpilation as an independent post-processing step. The method introduces three key techniques: a greedy qubit mapping strategy that minimizes pairwise distances between physical qubits, an adaptive Gray code selection combined with qubit swapping that optimizes the construction of uniformly controlled Rz gates for the target topology, and a heuristic for reducing CNOT gates by exploiting the structure of long-range CNOT ladders. We benchmark our method against TKet, Qiskit, and Pennylane on the 20-qubit IQM Garnet (square lattice) and the 156-qubit IBM Marrakesh (heavy-hex) architectures with qubit counts ranging from 3 to 11. Our method achieves CNOT count reductions of up to 36 percent on the IQM Garnet and up to 34 percent on the IBM Marrakesh compared to the best competing transpiler, while simultaneously achieving transpilation speedups of up to 553x. Furthermore, our method is the only one capable of transpiling circuits beyond 10 qubits within a 30-minute time limit across both architectures.

• The paper presents a hardware-aware synthesis strategy that integrates optimized block-ZXZ decomposition with dynamic qubit mapping to yield topology-minimal circuits.
• It employs greedy qubit mapping, Gray code selection, and adaptive qubit swapping to reduce CNOT counts by up to 36% and achieve dramatic runtime speedups.
• Quantitative benchmarks on IQM Garnet and IBM Marrakesh demonstrate scalable synthesis for n>10 qubits, significantly cutting compilation time.

Architecture-aware Unitary Synthesis for Quantum Circuit Compilation

Problem Statement and Motivation

The synthesis of arbitrary $n$-qubit unitary operators into hardware-executable circuits is a fundamental bottleneck for quantum computing. Optimal circuits minimize device-specific overheads, particularly two-qubit (CNOT) operations, due to their high error rates and long execution times on current superconducting qubit platforms. While optimal synthesis on all-to-all connected architectures is well studied, realistic devices (e.g., IQM Garnet with a square lattice, IBM Marrakesh with heavy-hex topology) have severe connectivity constraints. Conventional transpilers—Qiskit, TKET, Pennylane—address these by topology-agnostic synthesis followed by a routing-centric post-processing step, leading to significant CNOT overheads and scalability limitations. The presented work "Architecture-aware Unitary Synthesis" (2604.23777) overcomes these limitations by deeply integrating architectural considerations into every level of exact unitary synthesis.

Integrated, Hardware-conscious Synthesis Strategy

This work's core advancement is the fusion of the optimized block-ZXZ decomposition [blockzxz] with architectural awareness throughout the synthesis recursion. Rather than performing a generic decomposition followed by local routing, the method dynamically optimizes qubit mapping, CNOT laddering, and Gray code selection at every step to directly yield topology-minimal circuits.

Block-ZXZ Decomposition: The unitary is expressed recursively as multiplexers and uniformly controlled $R_z$ (UC) gates. Each recursion step creates four smaller unitaries and multiple UC gates, with further decomposition down to the two-qubit level. Single- and two-qubit unitaries are efficiently reduced via ZYZ and minimal CNOT constructions, respectively.

Greedy Qubit Mapping: At each recursion level, the method selects a subset of physical qubits $S$ that minimizes the sum of pairwise shortest-path distances according to the hardware's coupling map. For small $n$, an exhaustive strategy is used; for larger $n$, a fast greedy heuristic starts from the most central qubits by closeness centrality and iteratively expands $S$ by proximity.

Gray Code and CNOT Frequency Allocation: The decomposition of UC gates permits considerable freedom in control-target assignment. By analyzing all cyclic Gray codes and CNOT frequencies, the algorithm aligns high-frequency CNOTs with physically proximate qubits, drastically reducing routing overheads versus the default binary reflected code.

Adaptive Qubit Swapping: To further reduce control-target distances, the method evaluates swap sequences that physically reposition the target qubit of UC gates closer to controls before decomposing the UC operation, especially for the innermost levels of recursion.

Heuristic CNOT Ladder Optimizations: When CNOTs remain nonlocal, the method employs long-range CNOT "ladders" constructed along shortest hardware paths but exploits intermediate entanglement to opportunistically insert $R_z$ gates early and eliminate redundant local CNOTs. This heuristic is complemented with GraySynth [gray-synth] post-processing for any missed terms, ensuring exactness with minimal additional gates.

(Figure 1)

Figure 1: An example of the swapping procedure for a 6-qubit UC gate on the IQM Garnet quantum hardware; swapping target and control qubits enables more efficient routing for the UC gate.

Quantitative Performance: Gate Count and Runtime

Rigorous benchmarking was conducted on two representative architectures: the 20-qubit IQM Garnet (square lattice) and the 156-qubit IBM Marrakesh (heavy-hex). For randomly sampled unitaries of 3–11 qubits, the proposed method was compared to Qiskit, TKET, and Pennylane in terms of CNOT count and transpilation time.

Numerical Highlights:

• On the IQM Garnet, CNOT count reductions reached up to 36% (vs. Pennylane), 27% (vs. Qiskit), and 7% (vs. TKET).
• On IBM Marrakesh, reductions were as high as 34% (Pennylane), 19% (Qiskit), and 18% (TKET).
• Transpilation runtime speedups were dramatic: up to 553x (TKET), 39x (Qiskit), and 350x (Pennylane).
• The method was unique in successfully transpiling circuits with more than 10 qubits in under 30 minutes (whereas all other methods timed out or failed).
• Overhead versus the circuit-theoretic lower bound was 44.1% (IQM Garnet) and 58.1% (IBM Marrakesh), reflecting the substantial but bounded inevitable cost of limited connectivity.

Theoretical and Practical Implications

This architecture-conscious approach demonstrates that profound improvements in quantum circuit compilation are possible with globally-informed synthesis, rather than incremental post hoc routing. The separation between synthesis and routing, endemic to "compilation+transpilation" approaches, results in exponential scaling for both gate overhead and runtime—limitations that are circumvented by the integrated recursion proposed here.

Bold Claims Substantiated:

• This is the only method, among those compared, that can rapidly synthesize and transpile arbitrary exact unitaries for $n>10$ for realistic topologies.
• Simultaneously outperforms leading transpilers in both gate resource usage and wall-clock time.
• Empirically demonstrates that constant-factor gate overheads—relative to the theoretical lower bound—are achievable and stable as $n$ increases.

The implications are significant for NISQ and early fault-tolerant regimes: large reductions in CNOT count directly map to higher circuit fidelities, and fast compilation is essential for responsive quantum workflows. The transparent recursion and available open-source implementation provide a foundation for further extensions, including adaptation to native gate sets and interaction with error mitigation routines.

Future Directions

Potential avenues for advancing this line of work include:

• Generalization to mixed gate sets, e.g., using iSWAP, CZ, or arbitrary parametrized two-qubit gates as the hardware native set.
• Tighter integration with quantum algorithm toolchains, e.g., for hardware-efficient quantum state preparation [plesch-state-prep], QSVT, or quantum error correction circuits.
• Systematic investigation of the scaling and optimal strategies for even more constrained topologies or emerging architectures (e.g., photonic chips, ion traps).
• Exploitation of hardware calibration data (e.g., variable gate fidelities) in the greedy mapping and CNOT routing strategies to further reduce realistic error rates in compiled circuits.

Conclusion

"Architecture-aware Unitary Synthesis" (2604.23777) marks a substantial advancement in quantum circuit compilation by fusing hardware-topological considerations into every layer of exact unitary synthesis. Through hierarchical, hardware-adaptive recursion, optimal mapping, and informed gate sequence selection, it achieves consistently lower CNOT counts and dramatically reduced runtime versus established transpilers. The methodology sets a new standard for practical quantum circuit synthesis, making large, exact, hardware-executable unitaries tractable for contemporary and near-term quantum processors, and providing a scalable blueprint for next-generation compilation strategies in quantum computing.