Pulse Shaping to Mitigate the Impact of Device Imperfections in Field-Free Switching Using Combined Spin-Orbit and Spin-Transfer Torques

Abstract: Combining spin-orbit (SOT) and spin-transfer torques (STT) provides a practical approach for field-free switching in spin-orbit torque magnetic random-access memory (SOT-MRAM), a prerequisite for industrial deployment, but can compromise reliability through phenomena such as backhopping, especially in top-pinned stacks commonly used for SOT-MRAM. We investigate the write error rate (WER) of combined SOT + STT switching in top-pinned devices that are not optimized for STT switching. Experiments reveal clear indications of STT-induced backhopping and a pronounced field-free SOT switching asymmetry between AP-to-P and P-to-AP transitions. Our macrospin model, using two coupled Landau Lifshitz Gilbert equations for the free and the reference layers, qualitatively reproduces this asymmetry and reveals an intermediate loss-of-determinism regime in addition to the well-known backhopping region. Based on these simulations, we propose mitigation strategies and experimentally demonstrate that STT pulse shaping reduces WER and improves switching robustness in the presence of device imperfections.

• The paper shows that tailored STT and SOT pulse shaping significantly reduces write error rate and backhopping in top-pinned SOT-MRAM devices.
• Experimental data and macrospin simulations demonstrate that overlapping pulse strategies enhance deterministic switching performance by mitigating asymmetric thresholds.
• These findings highlight the critical role of device stack quality and precise pulse control for achieving reliable, field-free MRAM integration.

Pulse Shaping for Robust Field-Free Switching in SOT-MRAM with Device Imperfections

Motivation and Background

Spin-orbit torque MRAM (SOT-MRAM) is a leading candidate for cache-level memory applications, offering separate read/write paths and fast, reliable operation. To enable deterministic switching without an external symmetry-breaking field—crucial for large-scale CMOS integration—various schemes have been investigated, including exchange coupling, tilted anisotropy, and combining SOT with spin-transfer torque (STT). Of these, SOT+STT combinations are compatible with standard material systems and processes. Nevertheless, device imperfections, especially those typical in top-pinned MTJ stacks favored by SOT-MRAM, raise reliability issues such as backhopping and asymmetric switching thresholds. Understanding and mitigating these error mechanisms is essential for practical field-free SOT-MRAM deployment.

Experimental Characterization of Device Imperfections

The authors scrutinize top-pinned SOT-MRAM devices, measuring the write error rate (WER) for SOT, STT, and combined SOT+STT switching. Standard SOT-only switching with in-plane assist fields achieves deterministic behavior ($\text{WER} < 10^{-5}$), but removal of the external field exposes substantial AP-to-P vs. P-to-AP asymmetry and pronounced switching thresholds. STT-only switching also exhibits asymmetry and clear backhopping signatures, evidencing instability in the reference layer attributed to inadequate pinning—consistent with the poor stack order and grain texture in top-pinned MTJ fabrication.

Notably, irreversible changes in device behavior following high-amplitude STT pulses confirm the vulnerability of the reference layer. The WER characteristics shift after such events, indicating that internal magnetic fields and coupling effects are not only present but dynamically modifiable by switching operations.

Macrospin Modeling and Analysis

To systematize the observations, the study employs macrospin simulations using coupled Landau-Lifshitz-Gilbert (LLG) equations for the free and reference layers, incorporating SOT and STT terms as well as exchange coupling and field/damping-like SOT contributions. The model captures both deterministic switching regimes and error-prone regions, notably reproducing the experimentally observed asymmetry and backhopping phenomena.

In devices with significant interlayer coupling or reference layer tilt, the simulations reveal another regime: intermediate loss of determinism. This manifests as peculiar yellow bands in WER colormaps embedded in deterministic regions, depending on the direction and magnitude of reference layer tilt and coupling strength. These insights emphasize that stack quality (minimizing coupling, maximizing perpendicular magnetic anisotropy) is central to reliable operation.

Pulse Shaping Strategies and Experimental Validation

Guided by simulation results, the authors propose and test pulse engineering schemes to reduce WER and mitigate backhopping. Standard rectangular STT pulses at high voltage inject excessive energy, destabilizing the reference layer and promoting errors. By contrast, a shaped STT pulse—comprising a short high-voltage plateau and subsequent linear decay—reduces WER by at least an order of magnitude for both switching polarities.

Similarly, employing a two-step SOT pulse (subcritical follow-up to a main pulse) suppresses oscillatory switching behavior, especially in the presence of device imperfections. The combination of shaped STT and SOT pulses achieves robust field-free switching with improved determinism, low WER, and suppression of backhopping.

Additional experiments reveal the critical role of overlap between SOT and STT pulses: increasing overlap further lowers WER, while temporal separation counteracts the benefits of combined operation.

Numerical Results and Claims

• Standard rectangular STT pulses yield WER as low as 0.003 (P-to-AP) and 0.09 (AP-to-P); modified pulse shapes reduce WER by at least one decade for both transitions.
• Subcritical STT voltages combined with shaped pulses lower WER by more than an order of magnitude even prior to switching onset.
• Temporal overlap of SOT and STT pulses can decrease WER by a full decade compared to non-overlapped operation.
• Combined pulse shaping fully suppresses backhopping and loss-of-determinism regions—confirmed experimentally across all measured devices.

Implications and Future Directions

These results underscore that process-induced imperfections in reference layer pinning and interlayer coupling critically impact SOT-MRAM switching reliability. Pulse shaping offers a practical solution, but ultimate improvements will require further optimization of stack texture, layer growth, and device architecture. Enhanced modeling—possibly integrating micromagnetic simulations or atomistic defect descriptions—will illuminate remaining error sources.

The findings pave the way for industrial deployment of field-free SOT-MRAM using combined SOT+STT switching, contingent upon continued advances in fabrication, stack engineering, and pulse-control electronics. These techniques have broader implication for other spintronic devices where deterministic control in the presence of defects is essential.

Conclusion

Through systematic WER measurements and macrospin modeling, this paper establishes the detrimental effects of device imperfections in top-pinned SOT-MRAM and identifies pulse shaping as an effective mitigation strategy. The combination of tailored STT and SOT pulses achieves robust, low-error field-free magnetization switching, even in non-ideal stacks. This work informs practical approaches for reliable SOT-MRAM integration and reveals the critical importance of stack quality and dynamic pulse engineering for next-generation spintronic memory devices (2604.22574).