Spin Qubit Leapfrogging: Dynamics of shuttling electrons on top of another

Abstract: Spin shuttling has crystalized as a powerful and promising tool for establishing intermediate-range connectivity in semiconductor spin-qubit devices. Although experimental demonstrations have performed exceptionally well on different materials platforms, the question of how to handle areas of low valley splitting in silicon during shuttling remains unresolved. In this work, we explore the possibility of utilizing the valley degree of freedom, particularly in regions of low valley splitting, to allow mobile spin qubits to be shuttled through an occupied stationary quantum dot, thereby leapfrogging over the stationary electron. This not only grants a more enriched mobility for shuttled electrons, as it opens new possible routing paths, but also enables the implementation of an entangling SWAP$^γ$ two-qubit gate operation in the process. Simulating this process for different sets of parameters, we demonstrate the feasibility of such an operation and offer a unique use case for otherwise precarious regions of a quantum processor chip and propose a possible extension to the set of possible operations for silicon spin qubit devices.

• The paper demonstrates a valley-enabled leapfrogging protocol that shuttles electrons with high-fidelity spin transfer, enabling SWAPγ operations in a triple quantum dot.
• It uses adiabatic detuning pulses and Schrieffer-Wolff transformation to mitigate dephasing and leakage errors, achieving gate error probabilities around 4×10⁻³.
• Simulation results show robustness against outer dot asymmetry, suggesting practical applications in modular silicon quantum processors with dynamic qubit routing.

Spin Qubit Leapfrogging: Dynamics of Shuttling Electrons via Valley Excitations

Introduction and Background

The paper "Spin Qubit Leapfrogging: Dynamics of shuttling electrons on top of another" (2604.13760) addresses a pertinent challenge in semiconductor spin-qubit architectures: enabling coherent, high-fidelity intermediate-range transport of mobile spin qubits across quantum dots, particularly in silicon devices. The unique contribution lies in leveraging the valley degree of freedom—commonly regarded as a source of decoherence—to facilitate electron "leapfrogging" over a stationary electron occupying a quantum dot, thereby unlocking routing paths unavailable to pure-spin schemes and allowing a SWAP$^\gamma$ entangling operation during shuttling. This protocol circumvents the detrimental effects of low valley splitting, which typically threatens shuttling fidelity, thus repurposing a precarious chip region for constructive quantum gate operations.

Physical Model and Leapfrogging Protocol

The proposed mechanism models the system as a triple quantum dot (TQD) with fixed valley splittings and tunnel couplings. The central dot is persistently occupied by a stationary electron, while the mobile electron is shuttled from one outer dot to the other. The critical insight is that, due to the Pauli exclusion principle, triplet components of the two-electron wave function must transition into a valley-excited state to coexist on the central dot, gathering a phase relative to the singlet component determined by the valley splitting energy.

The protocol involves adiabatic detuning pulses controlling the chemical potentials, with waiting periods in doubly occupied (0,2,0) charge configurations to tune the acquired phase, implementing a SWAP$^\gamma$ gate. For triplet states, the leapfrogging operation is quantum mechanically distinct: they accumulate an additional valley-induced phase, effecting a nontrivial two-qubit entangling operation during transport. The Hamiltonian construction, based on detailed valley and spin-orbit physics, is treated via Schrieffer-Wolff transformation to exclude irrelevant charge configurations, and the simulation framework incorporates realistic device parameters and quasi-static noise sources.

Simulation Results and Error Analysis

Simulations utilizing QuTiP yield that adiabaticity is well-preserved throughout the protocol, with the electron successfully transferred through the occupied dot. Gate fidelity benchmarks are decomposed into state-transfer fidelity (measuring leakage) and dephasing fidelity (capturing accumulated phase errors due to charge noise). Notably, gate infidelities are computed for identity, SWAP, and $\sqrt{\text{SWAP}}$ gates, with the total error budget dominated by dephasing proportional to valley splitting, transfer leakage due to incomplete state transfer, and charge noise in tunnel couplings.

Strong numerical results include:

• Total gate error probabilities on the order of $4.2 \times 10^{-3}$ to $4.5 \times 10^{-3}$ for realistic parameter sets, well below typical error-correction thresholds.
• Gate operation times in the $\sim 50$–$70$ ns regime, consistent with standard two-qubit gates in Si devices.
• Gate fidelity is robust against asymmetry between outer dots, implying architectural flexibility.
• Use of tailored pulse profiles (two-speed sweeps) allows deterministic cancellation of dephasing from quasi-static noise in detuning.

Crucially, the simulation suggests the fidelity is maximized for low valley splitting in the central dot, with higher splittings exacerbating dephasing even with optimized pulse shaping. The error budget analysis demonstrates both transfer fidelity and dephasing fidelity contributions, and suggests that further improvements are achievable through experimental calibration and electronic noise suppression.

Theoretical and Practical Implications

Theoretically, the approach establishes a framework for exploiting valley states as computational resources in Si quantum processors, rather than treating them solely as sources of error. The leapfrogging operation enriches the toolkit for quantum routing, enabling direct interactions and gate implementations across occupied sites. This can facilitate modular chip architectures with “highway” lanes of mobile electrons, interconnecting dense qubit arrays, and simplifying qubit scheduling for circuit implementation.

Practically, the leapfrogging protocol provides a method to harness otherwise unusable regions of chips with low valley splitting, enhancing connectivity and gate repertoire. The high-fidelity SWAP$^\gamma$ operations are compatible with current surface code thresholds, and fabrication requirements are consistent with state-of-the-art Si devices. The protocol minimizes the need for rapidly addressable gates on tunnel and plunger signals, enabling aggressive filtering and further noise mitigation.

Future Directions

Several avenues remain for advancing the protocol:

• Pulse-shape optimization: Application of techniques such as GRAPE or other optimal control algorithms could further suppress leakage and dephasing.
• Experimental validation: Implementation in a Si TQD device, accompanied by full characterization of valley splitting landscapes, would empirically validate the theoretical fidelity projections.
• Integration with scalable architectures: Leapfrogging may serve as a core primitive for quantum processors with dynamic routing and reordering capabilities.
• Decoherence analysis: While the $(0,2,0)$ configuration is expected to possess favorable relaxation times, detailed studies of valley superposition decoherence, especially under varying valley splitting and charge noise profiles, are warranted.

Conclusion

By modeling and simulating the dynamics of shuttling an electron through an already occupied quantum dot in silicon, this work demonstrates the feasibility of the leapfrogging protocol as both a robust state-transfer mechanism and a generator of entangling SWAP$^\gamma$ gates. The method is resilient against typical levels of device noise and registers high fidelity under two distinct parameter regimes. It provides a versatile tool for exploiting dangerous regions of low valley splitting, with direct implications for future quantum processor architectures and routing strategies. The protocol is experimentally accessible and opens new directions in the practical exploitation of valley phenomena in semiconductor spin qubit platforms.