- The paper introduces a congestion marking mechanism that flags queueing delays by incrementing a marking counter to compensate for synchronization offset errors.
- It repurposes unused header fields like ECN bits in NTP and reserved bits in PTP, ensuring low-cost, backward-compatible improvements without deep packet inspection.
- Empirical evaluations on Tofino hardware and simulations demonstrate up to an 80% reduction in synchronization errors and significant performance gains in filtering techniques.
Improving Network Clock Synchronization by Marking Congestion
Introduction and Problem Statement
Precise network clock synchronization is essential for distributed systems requiring sub-microsecond alignment in domains such as cellular networks, IIoT, and transactional databases. Common protocols, NTP and PTP, rely on timestamp exchanges but are fundamentally susceptible to offset errors arising from asymmetric, congestion-induced queuing delays. Existing filtering strategies and hardware-supported transparent clocks (TCs) offer mitigation but at substantial implementation complexity and cost, particularly for switches and routers not designed for high-fidelity time correction.
This paper introduces a congestion marking mechanism, leveraging in-network signaling to flag synchronization packets experiencing queuing delays. By repurposing unused fields in packet headers, such as ECN bits in IP or reserved fields in NTP/PTP, switches increment a marking counter to annotate packets based on threshold-crossing events (Figure 1). Marked packets facilitate endpoint compensation—enabling offset estimation error reduction without altering protocol standards or deep packet inspection. The method exhibits strong numerical improvements: over a single hop, synchronization accuracy is enhanced by more than 80%, with low-pass filter performance improved by 90% in hardware measurements. Across multi-hop scenarios, RMS clock offset estimation error is reduced by 30–80%, depending on network conditions and filtering techniques.
Figure 1: Example working of the Marking Counter, incrementing based on congestion thresholds crossed at the switch egress.
Congestion Marking Mechanism
The proposed method generalizes ECN-style congestion indication. For each synchronization packet, switches check queue occupancy against a configurable set of R thresholds. The marking counter, encoded in a backward-compatible manner, is incremented at each threshold crossing. Endpoints use the count, multiplied by the minimum delay associated with the threshold (K∗), to compensate timestamps in offset calculations. This design is compatible with both IP and Ethernet deployments and fits seamlessly with the operation of NTP and PTP (Figure 2).

Figure 2: Mechanism of NTP (a) and PTP (b); both protocols use a four-timestamp offset estimation scheme vulnerable to delay asymmetry.
This congestion marking counter may be realized as a bit-shift or integer field, and can be split between forward and reverse path allocations in the case of PTP’s three-step synchronization handshake. The in-network marking is executed in the switch match-action pipeline using readily available metadata such as enqueue queue depth, enabling efficient implementation. Empirical measurements validate the precision of marking—for instance, Tofino-based P4 implementations yield delay indication accuracy within 5% of theoretical thresholds.
Implementation Complexity
Direct implementation of hardware-transparent clocks incurs prohibitive resource overhead in terms of pipeline depth, SRAM, and ALU operations. Experimental comparisons on Tofino hardware show that marking counters, especially bit-shift implementations, require fewer pipeline stages and dramatically less memory and computation than TCs, which often demand high-precision 64-bit arithmetic and stateful per-packet timestamp storage. Congestion marking, being lightweight and stateless, is thus highly practical for mass-produced switch architectures.
Statistical Analysis and Offset Estimation
The effectiveness of congestion marking is rooted in the statistical structure of queuing delays. The offset estimation error is given by the difference in queuing delays along the forward and reverse paths, ϵ=2(Respq​−Reqq​)​. Marking counters substantially reduce both the variance and bias of ϵ, as threshold-based marking leads to stochastic dominance in delay distributions. The authors rigorously detail the improvement conditions using general queuing distributions: variance reduction is guaranteed when the marking threshold K∗ enters a wide improvement region beyond twice the distribution mean, and bias improvement is ensured for distributions exhibiting larger means and CCDFs in the dominant direction.
Empirical and simulated datasets confirm the analytical predictions. (Figure 3) shows that the sum of per-hop queueing distributions leads to characteristic end-to-end delay distributions, which are efficiently reshaped by marking and endpoint compensation.
Figure 3: Sum of individual per-hop queuing distributions from source to sink determines the overall end-to-end delay distribution.
Evaluation: Practical Impact
OMNET++ simulation experiments demonstrate that short-lived, moderate UDP flows can induce significant delay asymmetries and large offset errors. Marking-based compensation, in conjunction with standard filtering, yields RMS error reductions up to 70%. Hardware measurements on a P4 Tofino platform—evaluated for marking accuracy under varying cross-traffic loads and queue thresholds—show misclassification rates below 3% for properly chosen marking granularity. Statistical filters, including min-RTT and median-delay, gain further improvement when used in tandem with marking, sometimes eliminating the need for filtering altogether.
Protocol Compatibility and Header Utilization
A key feature of the marking approach is backward compatibility. ECN bits can be exploited for NTP packets traversing the internet, while PTP headers offer unused reserved fields suitable for marking counters. Under NTP extensions, marking counter fields can be tuned to match network scale and granularity. The marking system coexists with legacy TC correction fields, and does not disrupt existing deployments—marked packets are ignored by non-updated endpoints and switches.
Implications and Future Directions
The results demonstrate that congestion marking fundamentally addresses the root cause of synchronization error due to PDV, while offering implementation simplicity unachievable by TCs. The method preserves protocol compatibility and offers robust improvement across diverse filtering and network configurations. Practically, this enables high-fidelity synchronization in networks ranging from data centers to industrial control systems without the need for expensive hardware upgrades or disruptive protocol changes.
Theoretically, congestion marking provides a mechanism for mapping in-network queuing effects onto statistical control of offset error, generalizable to other synchronization protocols and topologies. Future work may focus on adaptive threshold selection, more nuanced mappings between bytes and delay, integration into SDN control logic, and the use of ML for automated parameter optimization.
Conclusion
This paper establishes marking-based congestion indication as an efficient, scalable approach for improving network clock synchronization. By annotating packets experiencing queuing delay within switches, endpoints can reduce offset estimation errors without complex hardware support or protocol change. The mechanism achieves substantial numerical performance gains, and its analytical structure guarantees improvement under wide operational regimes. Congestion marking is poised to reshape the deployment of precision network synchronization for demanding distributed applications.