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L-PCN: A Point Cloud Accelerator Exploiting Spatial Locality through Octree-based Islandization

Published 12 Apr 2026 in cs.AR | (2604.10716v2)

Abstract: Existing Point Cloud Networks (PCNs) have proven to achieve great success in many point cloud tasks such as object part segmentation, shape classification, and so on. The most popular point-based PCNs are usually composed of two sequential steps: Data Structuring (DS) and Feature Computation (FC). In this paper, we first describe an important characteristic of the PCN-specific DS step that has not been addressed in existing PCN accelerators: the spatial locality resulting from overlapping points of the gathered point subsets. Using algorithm-hardware co-design, L-PCN (Locality-aware PCN) proposes two novel techniques to exploit this characteristic to reduce the large amount of repetitive operations in the overall PCN. The first of which is a point cloud partitioning technique, Octree-based Islandization. Using Octree-based adjacency gathering, a point cloud is partitioned into islands in L-PCN, where the point subsets inside the same island exhibit a strong spatial correlation. After partitioning, L-PCN performs the rest of PCN steps at the granularity of islands. The second method of L-PCN is scheduling the intra-island computation with a Hub-based Scheduling to exploit the intra-island data reuse by dynamically caching, updating, and reusing the repeated data. The two methods are implemented in an Islandization Unit, which can be seamlessly integrated into standard PCN workflow. Our evaluation shows that based on our methods for exploiting spatial locality, L-PCN achieves a theoretical reduction in feature fetching ranging from 55.2% to 93.8% and in feature computation ranging from 45.4% to 80.6% during the PCN process. For experimentation, prototype L-PCN accelerators are implemented on the Intel Arria 10 GX FPGA. Experimental results prove that with the Islandization Unit as a plug-in, state-of-the-art PCN accelerators can achieve an additional speedup ranging from 1.2x to 3.2x.

Summary

  • The paper introduces a hardware-software co-design that exploits octree-based islandization and hub-based scheduling to eliminate redundant point computations in PCNs.
  • It achieves dramatic reductions in feature fetching (up to 93.8%) and computation workload (up to 80.6%), delivering speedups of up to 3.2× and energy savings of up to 56%.
  • The design offers tunable accuracy-efficiency tradeoffs and broad applicability to 3D analytics, neural rendering, and other spatially-sparse data applications.

L-PCN: Architecture and Acceleration of Point Cloud Networks via Spatial Locality Exploitation

Introduction

L-PCN addresses redundant computation in point-based Point Cloud Networks (PCNs) arising from repeated processing of spatially overlapping point subsets generated during hierarchical data structuring. The work introduces two synergistic algorithm-hardware co-design techniques: Octree-based Islandization and Hub-based Scheduling—incorporated as an Islandization Unit—which partition the point cloud into spatially correlated islands and dynamically exploit intra-island data reuse. Empirical results on FPGA prototypes and large-scale benchmarks demonstrate that L-PCN provides substantial reductions in both memory bandwidth and feature computation workload, delivering speedups up to 3.2× across state-of-the-art PCN accelerators.

Spatial Locality and Redundancy in Point-based PCNs

The canonical point-based PCN workflow, instantiated in PointNet++ and DGCNN, comprises sequential Data Structuring (DS) and Feature Computation (FC) steps. DS forms local neighborhoods (point subsets) via spatial neighbor search (e.g., KNN, ball query), while FC processes these with MLPs. Critically, adjacent neighborhoods overlap heavily—over 90% in first-layer subsets—implying that most point features and MLP computations are redundantly fetched and evaluated multiple times.

Figure 1

Figure 1: Standard workflow and the two steps in the basic building block of point-based PCN: Data Structuring and Feature Computation.

The spatial overlap, as analyzed in PointNet++, is non-trivial; up to 87.5–93.75% of neighbor points are shared among neighboring point subsets across standard datasets and network depths.

Figure 2

Figure 2: Detailed breakdown and overlap analysis of two major Set Abstractions (i.e., two iterations of the PCN Building Block) of the benchmark PointNet++ PCN.

Unlike CNN or GCN accelerators, which can exploit data locality due to spatially contiguous memory layouts, PCN neighbor selection often employs FPS, leading to scattered processing and making conventional caching strategies ineffective.

L-PCN Architecture Overview

L-PCN inserts an Islandization Unit between the DSU and FCU, augmenting the point cloud processing pipeline to systematically detect and exploit intra-pointset spatial locality. The workflow proceeds as follows: (1) Sample central points, (2) gather neighbors and organize via Octree, (3) partition point subsets into spatially overlapping “Islands” using Octree adjacency, (4) schedule intra-island processing for maximal reuse via Hub-based Scheduling and overlap-aware caching.

Figure 3

Figure 3: Overall architecture of L-PCN.

Figure 4

Figure 4: (a) L-PCN workflow: adding Islandization Steps to exploit spatial locality. (b) Details of Data Structuring step, illustrating the overlap of points between point subsets.

Octree-based Islandization

Octree-based Islandization recursively partitions the point cloud such that each island consists of a set of point subsets whose central points are spatially adjacent (determined via Octree node proximity). Overlap pruning ensures that each point subset is exclusively assigned to a single island, maximizing intra-island spatial correlation.

Figure 5

Figure 5: (a) An example of picking five central points as Hub points (Hub P1 to Hub P5) from the Sampled Point Cloud. (b) Searching adjacent Octree nodes to gather neighboring central points for Hub P5 and create the Hub list P5. (c) Returning to the Input Point Cloud, partitioning it by forming L-PCN Islands based on the Hub Lists (d) An example of Island 5, which comprises eight point subsets. (e) The Island List used to represent the data of Island 5.

The Partitioning Module implements these operations efficiently in hardware, harnessing dual-parallel Octree Search Engines operating on sparsified Octree representations.

Figure 6

Figure 6: Architecture of Partitioning Module.

Hub-based Scheduling and Overlap Detection

Within each island, processing begins with the Hub point subset (maximally overlapping with all others). Its computation results are cached (Hub Cache). Subsequent subsets are scheduled so that, before MLP computation, their overlap with previously cached results is detected using Octree-based overlap detection. For overlapping points, prior MLP results are reused after applying a delta adjustment compensating the central point shift (to address result misalignment induced by preprocessing such as coordinate normalization).

Figure 7

Figure 7: Workflow of Hub-based Scheduling.

Figure 8

Figure 8: Detailed architecture and workflow of the Overlap Detection Module and Hub Cache.

The composite dataflow eliminates both redundant memory fetches and MLP compute for overlapping points, yielding multiplicative savings when overlap ratios are high.

Figure 9

Figure 9: Example of Data Reusing Method with overlap detection. In this example, the feature dimension of a point subset is changed from (32,6)(32, 6) to (32,128)(32, 128) during MLP layers. KK is the number of detected overlapping points.

Quantitative Results and Comparative Evaluation

Theoretical analysis indicates that L-PCN reduces feature fetching requirements by 55.2–93.8% and feature computation workload by 45.4–80.6% relative to baseline PCN accelerator methods, mapped across various PointNet++/DGCNN instantiations and benchmark datasets.

Figure 10

Figure 10

Figure 10: Theoretical workload optimization.

FPGA-implemented L-PCN prototypes, used as a plug-in to accurate (PointACC, HgPCN) and approximate (EdgePC, Crescent) DS accelerators, achieve measured speedups of 1.2×–3.2× in end-to-end inference latency, with energy reductions up to 56%. For large-scale models (PointNeXt, PointVector) and input sets exceeding 8×1038\times 10^3 points, L-PCN offers even more considerable gains due to higher neighborhood overlap.

Figure 11

Figure 11: Feature Computation speedup of GDPCA, L-PCN, and Mesorasi.

Figure 12

Figure 12: Theoretical workload optimization for PointNeXt and PointVector.

Figure 13

Figure 13: Performance Comparison of L-PCN prototype and FractalCloud.

L-PCN outperforms GDPCA, which relies on geometry-aware differential update but does not reduce the number of MLP computations, and Mesorasi, which utilizes delayed aggregation at the expense of increased memory access and serialization penalties. In delay-critical off-chip settings, L-PCN maintains its advantage due to runtime data reuse and minimal buffering demands.

Accuracy, Robustness, and Sensitivity

Although L-PCN's result delta compensation approximates some reused MLP results, the accuracy loss is consistently lower than that in Mesorasi (≤0.4% in most cases; rarely >1.5%), as approximation is restricted to overlapping points only; boundary points, which are more discriminative, are processed exactly.

Figure 14

Figure 14: Accuracy comparison among traditional method, L-PCN, and Mesorasi across different benchmarks.

Figure 15

Figure 15: Empirical analysis shows that non-overlapping (usually boundary) points more effectively capture the shape of the "airplane wings".

Sensitivity analysis shows a monotonic tradeoff: decreasing island size or Hub cache size reduces theoretical data reuse but yields marginally better accuracy due to increased exact computation, supporting tunable precision-efficiency for deployment requirements.

Figure 16

Figure 16: Sensitivity Study of Islandization hyperparameters.

ASIC Implementation and Overhead

A complete L-PCN ASIC design synthesized at 28nm/1GHz shows the Islandization Unit responsible for approximately 14% chip area and 10% dynamic power, but this is offset by drastic reductions in MLP compute array utilization and expensive DRAM accesses.

Figure 17

Figure 17: Detailed specifications and area/power breakdown of the L-PCN ASIC prototype.

Implications and Future Work

L-PCN’s core methodology—hardware-supported spatial locality exploitation via runtime partitioning and fine-grained dynamic reuse scheduling—is generally applicable to point cloud analytics beyond classification/segmentation, including emerging workloads in 3D Gaussian rendering and large-scale geometric vision. The architectural principles and dataflow optimizations port directly to other memory- and compute-bound pipelines involving spatially-sparse or neighbor-aggregated data, as in sparse CNNs or GCNs. Adaptive, on-the-fly partitioning and selective precision modulation open compelling avenues for next-generation neural accelerators optimized for multi-modal 3D perception and AR/VR workloads.

Conclusion

L-PCN formalizes and realizes an algorithm-hardware co-design framework for reducing intrinsic redundancy in hierarchical PCN workloads by exploiting high levels of spatial locality at the point subset level. The Islandization Unit, combining Octree-based clustering and dynamic hub-based scheduling, achieves substantial savings in both memory and compute across standard and large-scale benchmarks, with accuracy-sensitive, tunable tradeoffs. Its broad extensibility across 3D analytics, neural rendering, and related domains underscores the relevance of locality-centric hardware designs in future high-throughput vision systems (2604.10716).

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