L-SPINE: A Low-Precision SIMD Spiking Neural Compute Engine for Resource-efficient Edge Inference

Abstract: Spiking Neural Networks (SNNs) offer a promising solution for energy-efficient edge intelligence; however, their hardware deployment is constrained by memory overhead, inefficient scaling operations, and limited parallelism. This work proposes L-SPINE, a low-precision SIMD-enabled spiking neural compute engine for efficient edge inference. The architecture features a unified multi-precision datapath supporting 2-bit, 4-bit, and 8-bit operations, leveraging a multiplier-less shift-add model for neuron dynamics and synaptic accumulation. Implemented on an AMD VC707 FPGA, the proposed neuron requires only 459 LUTs and 408 FFs, achieving a critical delay of 0.39 ns and 4.2 mW power. At the system level, L-SPINE achieves 46.37K LUTs, 30.4K FFs, 2.38 ms latency, and 0.54 W power. Compared to CPU and GPU platforms, it reduces inference latency from seconds to milliseconds, achieving an up to three orders-of-magnitude improvement in energy efficiency. Quantisation analysis shows that INT2/INT4 configurations significantly reduce memory footprint with minimal accuracy loss. These results establish L-SPINE as a scalable and efficient solution for real-time edge SNN deployment.

• The paper presents L-SPINE, a low-precision SIMD compute engine that eliminates multipliers using a shift-add design for efficient SNN inference.
• The methodology integrates configurable 2-, 4-, and 8-bit quantization with FPGA deployment, achieving dramatic reductions in energy and resource use.
• Comparative evaluations show L-SPINE reduces latency and resource utilization while maintaining robust inference performance compared to traditional designs.

L-SPINE: A Low-Precision SIMD Spiking Neural Compute Engine for Resource-efficient Edge Inference

Introduction

L-SPINE introduces a hardware-efficient, low-precision SIMD (Single Instruction Multiple Data) compute engine tailored for Spiking Neural Networks (SNNs) targeting real-time, resource-constrained edge inference. SNNs' event-driven computation and temporal coding afford compelling energy savings, but robust, scalable deployment faces constraints from memory bottlenecks, inefficient scaling operations, and limited parallelism. L-SPINE addresses these gaps with a unified multi-precision datapath, a multiplier-less shift-add mechanism for neuron dynamics, configurable quantization, and streamlined integration on FPGAs.

Architectural Contributions

L-SPINE’s architecture is built on several core components: a tightly coupled RISC-V controller, spike encoding modules, and a 2D array of SIMD-enabled neuron compute engines (NCEs). The system efficiently orchestrates spike-based dataflow, membrane potential updates, and synaptic computation to optimize for both parallelism and energy efficiency.

Figure 1: System-level architecture of the proposed L-SPINE accelerator integrating pico-rv32 RISC-V, spike encoding modules, and a 2D SIMD-enabled neuron processing array for efficient SNN inference.

Central to the design is the NCE, which supports configurable 2-, 4-, and 8-bit MAC operations within a unified datapath. This is realized via a reconfigurable shift-add architecture, enabling the mapping of multiple low-bit operations in parallel (16× INT2, 4× INT4, 1× INT8), dynamically selectable on-the-fly. The NCE eliminates the need for digital multipliers, employing bit-wise shift and accumulation for membrane dynamics (leakage, integration, reset, thresholding) and spike-based input processing.

Figure 2: Detailed datapath for Proposed SIMD-enabled multi-precision compute engine supporting configurable 16x 2-bit, 4x 4-bit, and 1x 8-bit operations using a reconfigurable shift-add logic integrated in LIF neuron computation.

This architecture allows efficient parallel processing and superior area/power utilization compared to prior designs based on multiplierless but less flexible dataflows (e.g., CORDIC-based or LUT-based implementations). Additionally, dataflow optimizations minimize external memory accesses, exploiting locality in spike data and synaptic weights.

Methodology and Evaluation Flow

The system workflow includes:

• SNN training using standard BP/STDP,
• Aggressive low-bit quantization (2-, 4-, 8-bit parameters),
• Hardware mapping and scheduling for SIMD-enabled NCEs,
• FPGA-based deployment and evaluation.

Quantized model weights and neuron parameters are encoded and tiled onto the NCE array for maximum hardware utilization. Cycle-accurate simulation, hardware synthesis, and empirical analysis inform iterative architectural refinement.

Figure 3: Design and evaluation flow of the proposed L-SPINE architecture, including SNN training, quantization, hardware mapping, and FPGA-based validation.

Quantization and Accuracy Trade-offs

Quantitative comparison with state-of-the-art SNN quantization (STBP, ADMM, truncation) demonstrates that L-SPINE trades only marginal accuracy for dramatic savings in area, energy, and latency at low-bit precision. INT2/INT4 configurations provide particularly favorable memory-accuracy trade-offs, significantly reducing footprint while maintaining functional performance for edge applications.

Figure 4: Comparison of accuracy and memory footprint with the state-of-the-art SNN quantisation, STBP, ADMM, and Trunc methods.

Accuracy analysis across INT2/INT4/INT8 versus FP32 precision confirms the efficacy of L-SPINE’s datapath: INT8 closely matches FP32, while INT2/INT4 exhibit graceful degradation appropriate for many edge scenarios.

Figure 5: Impact of precision scaling on SNN accuracy across INT2, INT4, INT8, and FP32 configurations.

Hardware Metrics and Comparative Results

The L-SPINE neuron architecture, implemented on a Xilinx VC707 FPGA, sets state-of-the-art marks in resource and energy efficiency: 459 LUTs, 408 FFs per neuron, critical delay of 0.39 ns, and 4.2 mW per neuron. System-level performance is equally compelling: 46.37K LUTs, 30.4K FFs, 2.38 ms inference latency, and 0.54 W power.

Compared to prior FPGA/ASIC SNN accelerators—many of which are tied to higher-precision, less flexible, or non-SIMD designs—L-SPINE consistently reduces resource utilization, surpasses throughput, and yields up to three orders-of-magnitude energy savings. Latency for standard deep nets (e.g., VGG-16/ResNet-18) is reduced from seconds (CPU/GPU) to milliseconds, at a tiny power envelope.

Implications and Future Directions

The demonstrated architecture offers immediate benefits for embedded, autonomous, and wearable devices processing event streams in real time. L-SPINE’s support for scalable multi-precision and its multiplier-less design position it favorably for integration in adaptive or reconfigurable edge AI frameworks, where both workload adaptability and energy proportionality are crucial.

Theoretically, the work provides a reference architecture bridging algorithmic quantization and resource-aware SNN hardware, demonstrating that aggressive quantization and smart datapath design need not compromise application-level accuracy. Practically, the configuration flexibility supports both current SNN workloads and prospective event-driven edge-AI paradigms.

Anticipated future developments include:

• Layer-adaptive precision scaling for further energy-accuracy trade-offs,
• Integration with emerging non-volatile or in-memory compute fabrics,
• Exploration of more complex SNN models and emerging neuromorphic applications.

Conclusion

L-SPINE presents a SIMD-enabled, low-precision SNN compute engine that is both area/power efficient and highly performant, closing the gap between algorithmic advances in low-bit SNNs and scalable, real-time deployment on edge platforms. The methodology and results outlined provide a robust framework for continued innovation in hardware-efficient neuromorphic inference.

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