Biologically Realistic Dynamics for Nonlinear Classification in CMOS+X Neurons

Abstract: Spiking neural networks encode information in spike timing and offer a pathway toward energy efficient artificial intelligence. However, a key challenge in spiking neural networks is realizing nonlinear and expressive computation in compact, energy-efficient hardware without relying on additional circuit complexity. In this work, we examine nonlinear computation in a CMOS+X spiking neuron implemented with a magnetic tunnel junction connected in series with an NMOS transistor. Circuit simulations of a multilayer network solving the XOR classification problem show that three intrinsic neuronal properties enable nonlinear behavior: threshold activation, response latency, and absolute refraction. Threshold activation determines which neurons participate in computation, response latency shifts spike timing, and absolute refraction suppresses subsequent spikes. These results show that magnetization dynamics of MTJ devices can support nonlinear computation in compact neuromorphic hardware.

• The paper shows that the hybrid CMOS+MTJ neuron architecture naturally replicates biological threshold activation, response latency, and refractoriness to solve linearly inseparable tasks like XOR classification.
• It utilizes detailed simulations linking MTJ physical properties to network-level spike-timing dynamics and verifies an analog spike-timing-based gradient descent learning rule.
• The approach reduces circuit complexity and power consumption, paving the way for scalable, biologically plausible neuromorphic computing in edge and embedded AI applications.

Biologically Realistic Nonlinear Computation in CMOS+MTJ Spiking Neurons

Introduction

This paper addresses a central challenge in neuromorphic computing: realizing expressive, nonlinear computation within energy- and area-efficient hardware suitable for edge and embedded artificial intelligence applications. Standard SNNs are attractive for their sparse, event-driven computation, but typically require additional circuit complexity to achieve nonlinear processing capabilities comparable to biological neurons. The work examines a minimal CMOS+X neuron—a series NMOS transistor and magnetic tunnel junction (NMOS+MTJ)—demonstrating through detailed simulations that key biologically realistic dynamics intrinsic to this device are sufficient to solve nonlinear tasks. Focusing on the XOR benchmark, the analysis connects device-level MTJ physics to network-level computational functions, elucidating how thresholding, latency, and refractoriness emerge and interact to enable linearly inseparable classification.

NMOS+MTJ Spiking Neuron: Device Architecture and Dynamics

The NMOS+MTJ neuron comprises a conventional NMOS transistor in series with a magnetic tunnel junction, structurally similar to commercial 1T-1MTJ MRAM. The core nonlinear behavior—spike generation, threshold detection, variable response latency, and refraction—arises directly from the spin-transfer torque-driven magnetization dynamics of the MTJ free layer.

Figure 1: Schematic of two NMOS+MTJ neurons connected by a tunable synapse, with spike generation and transmission governed by intrinsic device physics.

Unlike most silicon neuron implementations, the NMOS+MTJ circuit does not require explicit threshold detectors or refractory timers; these are instead emergent properties of the physical system. The MTJ acts as a nonlinear element whose resistance switches only when input-induced current exceeds a critical threshold, and whose subsequent magnetization relaxation period naturally enforces refractoriness. Synaptic strength is realized via the gain of an analog voltage amplifier, maintaining compatibility with conventional CMOS for scalability.

Architecture for Nonlinear Task: XOR Network Realization

To analyze network-level nonlinearity and learning, the authors instantiate an XOR classification network as a canonical test case not solvable by single-layer perceptrons. The architecture includes input encoding neurons, a hidden layer of NMOS+MTJ neurons, an output neuron, and a bias term, connected by trainable analog synapses.

Figure 2: Topology of the NMOS+MTJ-based XOR classification network; input bits are converted to spike events, processed through a hidden layer and weighted synapses, and decoded by the timing of the output neuron spike.

The network operates in a single-spike regime for each neuron, allowing precise control and observation of spike timing. Output is encoded by the timing of the output neuron spike: $t = 2$ ns for logical 0, $t = 2.5$ ns for logical 1, aligning with the convention in prior NMOS+MTJ work. Training uses an analog spike-timing-based gradient descent that updates synaptic gains to minimize a quadratic loss on output spike timing. This is notable for demonstrating that the learning rule and network operation are not only theoretically compatible with, but can be efficiently realized in, mixed-signal hardware.

Biologically Inspired Dynamics as Computational Primitives

Strong empirical results are presented substantiating the claim that three key dynamical features—threshold activation, response latency, and absolute refraction—are jointly sufficient for nonlinear computation in hardware SNNs:

Threshold Activation: The network exhibits an all-or-nothing response, with spiking dependent on whether input surpasses a sharply defined threshold. This filters subthreshold noise and enforces sparse computation—essential for energy efficiency and robustness.

Response Latency: Spike latency depends on input amplitude. Stronger currents induce faster switching, yielding earlier spikes; weaker near-threshold inputs result in longer delays. This property encodes analog input strength into temporal patterns, thus enabling linearly inseparable tasks (as in XOR) to be solved by timing-based computation.

Figure 3: Simulated spike responses for separate XOR input rows; threshold and latency dynamics produce distinct output spike timings representing different logical outcomes.

Absolute Refraction: After firing, neurons enter a refractory window determined by ongoing MTJ free-layer dynamics. During this period, additional above-threshold inputs do not elicit further spikes, suppressing spurious output and enabling time-domain winner-take-all selection.

Figure 4: Simulation showing the effect of refractoriness; despite temporally overlapping above-threshold inputs, only one output spike is emitted due to absolute refraction in the MTJ-based neuron.

These features, when combined, provide sufficient nonlinearity for multilayer temporal computation with no need for explicit digital control or additional analog subcircuits, significantly enhancing efficiency and design simplicity.

Practical and Theoretical Implications

The demonstrated ability to solve a linearly inseparable classification problem in a compact, CMOS-compatible SNN architecture validates the claim that device-level biologically realistic properties are not mere analogies but can serve as primary computational mechanisms. The implications are significant: minimal hybrid (CMOS+MTJ) circuits can match the key nonlinear behaviors of large, power-hungry digital systems. Given the physical basis of thresholding, latency, and refraction, such devices can be massively parallelized for dense on-chip learning and inference.

Additionally, the integration compatibility with mature MRAM process flows supports practical scalability. On the theoretical side, this paradigm operationalizes the concept of computation emerging from physical constraints and dynamics, moving away from heavy reliance on auxiliary circuitry.

Outlook and Future Directions

Potential extensions arise in two domains. First, there are obvious applications in low-power edge AI hardware, where energy and area constraints preclude large digital logic blocks. Second, further theoretical exploration is warranted to characterize the computational complexity and expressivity achievable by larger networks of NMOS+MTJ neurons, especially when network topologies and synaptic plasticity mechanisms are varied. Scaling the demonstrated training methods to deeper or recurrent networks presents both opportunities and challenges. Additional study should focus on robustness to device mismatch, noise, and process variation, as well as on hybrid integration with other emerging memory technologies.

Conclusion

This work substantiates that the essential features of nonlinear biological computation—sharply defined thresholding, input-dependent latency, and strict atomic output spikes—can be realized within a minimalist NMOS+MTJ circuit without auxiliary complexity. Simulation results on the XOR problem support that these features, as intrinsic device properties, are jointly sufficient for nonlinear SNN computation and trainable analog learning. The approach materially advances the case for scalable, low-power, biologically plausible AI hardware architectures that leverage physical dynamics rather than engineering new control logic for each required property.