E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis (2504.11574v2)

Abstract: In technology mapping, the quality of the final implementation heavily relies on the circuit structure after technology-independent optimization. Recent studies have introduced equality saturation as a novel optimization approach. However, its efficiency remains a hurdle against its wide adoption in logic synthesis. This paper proposes a highly scalable and efficient framework named E-morphic. It is the first work that employs equality saturation for resynthesis after conventional technology-independent logic optimizations, enabling structure exploration before technology mapping. Powered by several key enhancements to the equality saturation framework, such as direct e-graph-circuit conversion, solution-space pruning, and simulated annealing for e-graph extraction, this approach not only improves the scalability and extraction efficiency of e-graph rewriting but also addresses the structural bias issue present in conventional logic synthesis flows through parallel structural exploration and resynthesis. Experiments show that, compared to the state-of-the-art delay optimization flow in ABC, E-morphic on average achieves 12.54% area saving and 7.29% delay reduction on the large-scale circuits in the EPFL benchmark.

Scalable Equality Saturation for Structural Exploration in Logic Synthesis

The paper "Scalable Equality Saturation for Structural Exploration in Logic Synthesis" addresses significant shortcomings in existing logic synthesis methodologies, focusing on the application of equality saturation for effective structural exploration prior to technology mapping. Equality saturation, a method of non-destructive rewriting, has emerged as a promising approach in various optimization domains. However, its effectiveness and scalability in logic synthesis have historically been limited due to efficiency constraints. This paper proposes an innovative framework to surmount these barriers, enabling broader adoption across large-scale Boolean logic optimization scenarios.

Key Contributions

The crux of this paper is the introduction of a novel framework, named "Morphic", that enhances the scalability and efficiency of equality saturation in logic synthesis. The framework incorporates several pivotal innovations:

1. Parallel Structural Exploration: This approach leverages equality saturation in resynthesis after conventional technology-independent logic optimizations, allowing for comprehensive structural exploration prior to technology mapping. By reducing the dependence on initial circuit structures, it addresses the prevalent issue of structural bias.
2. Advanced Extraction Techniques: Solution space pruning and simulated annealing are integrated to refine the extraction process, offering improved scalability and reduced computational overhead. These methods significantly enhance the ability to explore diverse logical structures efficiently.
3. DAG-to-DAG Conversion: The framework employs direct conversion between circuits and e-graphs without intermediate representations like S-expressions, profoundly improving conversion efficiency and facilitating faster evaluations.
4. Machine Learning Integration: Morphic incorporates machine learning-based cost estimation models for rapid quality assessment, thus expediting the optimization process further.

Experimental Validation

The experimental results presented in the paper underscore the efficacy of the proposed approach. Compared to existing state-of-the-art delay optimization flows, Morphic achieves an average area saving of 12.54% and a delay reduction of 7.29% on large-scale circuits from the EPFL benchmark suite. This reflects substantial improvements in both area efficiency and delay reduction, achieved with moderate runtime overhead.

The framework's ability to efficiently handle large-scale circuits is particularly noteworthy. Prior limitations in scalability and conversion speed, which rendered most previously used methods impractical for large circuits, are effectively addressed. The direct DAG-to-DAG conversion methodology is shown to drastically reduce conversion times from orders of magnitude down to mere seconds, even for circuits with tens of thousands of nodes.

Implications and Future Directions

This research carries significant implications for logic synthesis practices. By overcoming traditional structural bias through extensive structural exploration, Morphic potentially enhances the quality of technology mapping results while reducing the need for complex heuristic approaches. The integration of machine learning models for cost estimation enables further acceleration of the synthesis process, offering a promising direction for future enhancements in automated logic design frameworks.

The proposed advancements are not confined to logic synthesis alone. They portend broader applications of equality saturation across diverse optimization scenarios, particularly those demanding extensive design space exploration without compromise on scalability.

Morphic presents a paradigm shift in logic synthesis, redefining structural optimization strategies and paving the way for future developments in heuristic and algorithmic logic synthesis. The demonstrated capabilities in improving synthesis efficiency and effectiveness may inspire further exploration into applying similar methodologies in adjacent fields of electronic design automation.