E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (2403.14242v2)
Abstract: Logic synthesis plays a crucial role in the digital design flow. It has a decisive influence on the final Quality of Results (QoR) of the circuit implementations. However, existing multi-level logic optimization algorithms often employ greedy approaches with a series of local optimization steps. Each step breaks the circuit into small pieces (e.g., k-feasible cuts) and applies incremental changes to individual pieces separately. These local optimization steps could limit the exploration space and may miss opportunities for significant improvements. To address the limitation, this paper proposes using e-graph in logic synthesis. The new workflow, named Esyn, makes use of the well-established e-graph infrastructure to efficiently perform logic rewriting. It explores a diverse set of equivalent Boolean representations while allowing technology-aware cost functions to better support delay-oriented and area-oriented logic synthesis. Experiments over a wide range of benchmark designs show our proposed logic optimization approach reaches a wider design space compared to the commonly used AIG-based logic synthesis flow. It achieves on average 15.29% delay saving in delay-oriented synthesis and 6.42% area saving for area-oriented synthesis.
- The EPFL combinational benchmark suite. In IWLS.
- Majority-Inverter Graph: A New Paradigm for Logic Optimization. TCAD 35, 5 (2016), 806–819.
- Robert Brayton and Alan Mishchenko. 2010. ABC: An Academic Industrial-Strength Verification Tool. In Computer Aided Verification. Springer, 24–40.
- Franc Brglez. 1985. A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran. In Proc. Intl. Symp. Circuits and Systems, 1985.
- ASAP7: A 7-nm finFET predictive process design kit. Microelectronics Journal 53 (2016), 105–115.
- RT-level ITC’99 benchmarks and first ATPG results. IEEE Design & Test 17, 3 (2000), 44–53.
- Automatic Datapath Optimization using E-graphs. In ARITH. IEEE, 43–50.
- Datapath Verification via Word-Level E-Graph Rewriting. arXivL preprint arXiv:2308.00431 (2023).
- Leonardo De Moura and Nikolaj Bjørner. 2008. Z3: An efficient SMT solver. In International conference on Tools and Algorithms for the Construction and Analysis of Systems. Springer, 337–340.
- A novel basis for logic rewriting. In ASP-DAC. 151–156.
- On XAIG Rewriting. In IWLS. 89–96.
- GenMul: Generating architecturally complex multipliers to challenge formal verification tools. In Recent Findings in Boolean Techniques: Selected Papers from the 14th International Workshop on Boolean Problems. Springer, 177–191.
- Alan Mishchenko and Robert Brayton. 2006. Scalable Logic Synthesis using a Simple Circuit Structure. In IWLS, Vol. 6. 15–22.
- Global Delay Optimization using Structural Choices. In FPGA. 181–184.
- DAG-Aware AIG Rewriting a Fresh Look at Combinational Logic Synthesis. In DAC. ACM, 532–535.
- Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis. In ASP-DAC. 395–402.
- How Good Is Your Verilog RTL Code? A Quick Answer from Machine Learning. In ICCAD. 1–9.
- Equality Saturation: A New Approach to Optimization. In POPL. ACM, New York, NY, USA, 264–276.
- Impress: Large Integer Multiplication Expression Rewriting for FPGA HLS. In FCCM. IEEE, 1–10.
- Equality Saturation for Datapath Synthesis: A Pathway to Pareto Optimality. In 2023 60th ACM/IEEE Design Automation Conference (DAC). IEEE, 1–2.
- Egg: Fast and Extensible Equality Saturation. In POPL, Vol. 5. ACM, New York, NY, USA, 1–29.
- S Yang. 1989. Logic synthesis and optimization benchmarks: Technical report. In IWLS. 14.
- Saeyang Yang. 1991. Logic synthesis and optimization benchmarks user guide: version 3.0. Citeseer.