Establish whether memory-side caches coalesce GPU read-bypass requests

Establish whether the memory-side cache on the Intel Lunar platform coalesces fine-grained GPU Read-Bypass requests and thereby explains their superior performance for large memory regions, in contrast to the performance degradation observed on the memory-side-cache-free Intel Arrow platform.

Background

The study compares Read-Bypass with driver-triggered Read-after-Invalidation on Intel Arc GPUs. Read-Bypass slightly outperforms Read-after-Invalidation on Lunar, which includes a memory-side cache, but nearly doubles read time for regions larger than 16 MB on Arrow, which lacks such a cache.

The authors attribute this platform difference to a hypothesized coalescing effect of the memory-side cache. The paper does not directly verify that mechanism.

References

We hypothesize that the MSC coalesces fine-grained R${_\text{B}$} requests, reducing pressure on the memory controller.

— Characterizing CPU-GPU Memory Sharing over Unified Memory Architecture  (2610.13125 - Yang et al., 9 Oct 2026) in Section 5.2.2, subsection “Intel Arc GPUs”