Explain the performance cost of two-way coherence on DGX Spark

Determine whether the observed performance cost of two-way cache coherence on NVIDIA DGX Spark results from attaching the GPU as a fully coherent AMBA CHI request node that incurs directory registration, ownership acquisition, and eviction-related coherence traffic for write-back GPU cache lines.

Background

The DGX Spark extension evaluates a unified-memory platform with two-way CPU–GPU coherence. The measurements show that two-way coherence can reduce throughput for large streaming GPU accesses when the shared memory uses write-back caching, while uncached accesses are largely insensitive to the coherence configuration.

The paper proposes an architectural explanation based on AMBA CHI request-node roles and the additional coherence traffic incurred by a fully coherent GPU cache. This explanation is explicitly presented as a hypothesis rather than a demonstrated result.

References

We hypothesize that this pattern is a direct consequence of implementing two-way CC using the AMBA CHI protocol.

— Characterizing CPU-GPU Memory Sharing over Unified Memory Architecture  (2610.13125 - Yang et al., 9 Oct 2026) in Appendix A, subsection “Two-way coherence”