Microarchitecture-Aware Binary Translation

Design binary translators that effectively account for CPU microarchitecture and investigate the intricate relationship between translated binary code and CPU pipeline behavior in order to reduce execution overhead.

Background

The evaluation shows that LLMSbt-translated binaries may execute more instructions and consume more CPU cycles than native binaries, but the resulting overhead is not proportional to instruction count. The authors attribute this variation to microarchitectural factors such as pipelining, branch prediction, caching, and memory-access behavior. In particular, translated code generally exhibits more cache misses, while native code tends to experience more branch misses; poor cache efficiency is identified as a significant source of overhead for some workloads. The paper therefore leaves open the broader problem of designing binary translators that explicitly account for target-CPU microarchitecture and of characterizing how translated instruction sequences interact with CPU pipeline behavior.

References

Designing a binary translator that effectively accounts for the microarchitecture remains an open challenge, and investigating the intricate relationship between binary code and CPU pipeline behavior is an intriguing topic for future research.

— No More Translation at Runtime: LLM-Empowered Static Binary Translation  (2610.05999 - Liu et al., 5 Oct 2026) in Section 5.3, subsection “Performance Analysis” (labeled “Performance Analysis”)