Determine the escape-stage impact on cultivation-scheme comparisons

Determine the exact effect of the fault-tolerant escape stage on the logical error rates and relative performance of the regular-surface-code and partially fault-tolerant rotated-surface-code fold-transversal magic state cultivation schemes.

Background

The paper compares cultivation costs and logical error rates during the noisy state preparation and cultivation stages, excluding the subsequent escape stage. The partially fault-tolerant rotated-surface-code fold-transversal S-gate schemes have lower expected space-time overhead but higher logical error rates than the regular-surface-code scheme.

Because the escape stage is fault tolerant and can be evaluated using simulator-agnostic hand-off methods, its inclusion may alter the discrepancy between the schemes. The paper does not quantify this effect and explicitly leaves it unresolved.