Vertical Adiabatic Couplers (VACs)

• Vertical Adiabatic Couplers (VACs) are integrated photonic devices that perform efficient, broadband vertical mode transformation between silicon wire and III-V waveguide stacks.
• They use a unique bi-sectional, tapered design that omits the p-InP cladding in the first section to enable ultracompact device footprints and robust mode evolution.
• Performance metrics show >95% coupling efficiency, low insertion (<0.22 dB) and reflection loss (< -40 dB), with excellent tolerance to fabrication imperfections.

A Vertical Adiabatic Coupler (VAC) is an integrated photonic device designed for efficient, broadband, and low-loss vertical optical mode transformation between a silicon-on-insulator (SOI) wire waveguide and a heterogeneous Si/III-V waveguide stack. In the context of heterogeneous silicon photonics, the VAC performs an adiabatic mode transformation that is robust to fabrication tolerances and geometric nonidealities, while offering ultracompact device footprints. The salient realization involves a bi-sectional, semi-three-dimensional (semi-3D) tapered structure exclusively patterned in the III-V layer stack, enabling fundamentally improved performance in Si/III-V heterogeneous integration scenarios for lasers, amplifiers, and modulators (Huang et al., 2014).

1. Device Structure and Layer Stack

The VAC is built on a precise layer stack optimized for vertical mode transformation:

• Substrate and Waveguide: A bulk Si substrate supports a buried SiO₂ (BOX) layer of 2 µm thickness ($n \approx 1.445$). The optical input is a single-mode SOI wire waveguide: width $W_\mathrm{Si} = 600\,\mathrm{nm}$, thickness $t_\mathrm{Si} = 220\,\mathrm{nm}$ ($n = 3.455$).
• Bonding Layer: Benzocyclobutene (BCB) bonding layer separates SOI and III-V epitaxial stacks. Thickness $h_\mathrm{BCB} = 0$--$100\,\mathrm{nm}$ ($n=1.543$).
• III-V Epitaxy:
  • $150\,\mathrm{nm}$ n-InP cap ($n=3.1667$)
  • $100\,\mathrm{nm}$ SCH₂ ($W_\mathrm{Si} = 600\,\mathrm{nm}$0)
  • $W_\mathrm{Si} = 600\,\mathrm{nm}$1 multiple quantum well (MQW) region ($W_\mathrm{Si} = 600\,\mathrm{nm}$2)
  • $W_\mathrm{Si} = 600\,\mathrm{nm}$3 SCH₁ ($W_\mathrm{Si} = 600\,\mathrm{nm}$4)
  • $W_\mathrm{Si} = 600\,\mathrm{nm}$5 p-InP cladding (present only in terminal section)
  • $W_\mathrm{Si} = 600\,\mathrm{nm}$6 p⁺-InGaAs contact ($W_\mathrm{Si} = 600\,\mathrm{nm}$7)

At the output, the hybrid III-V mesa's width is $W_\mathrm{Si} = 600\,\mathrm{nm}$8. The SOI waveguide is kept straight across the coupler, while the III-V mesa is patterned to form the bi-sectional taper.

2. Bi-Sectional Tapered Coupler Design

VAC employs a two-section tapered transition within the III-V layers to realize efficient adiabatic transformation:

• Section 1: The SCH/MQW stack (without p-InP cladding) tapers from a narrow tip ($W_\mathrm{Si} = 600\,\mathrm{nm}$9) to $t_\mathrm{Si} = 220\,\mathrm{nm}$0 over length $t_\mathrm{Si} = 220\,\mathrm{nm}$1. High-order mode excitation in the thick p-cladding is suppressed by omitting p-InP in this segment, ensuring the fundamental optical mode evolves without crosstalk.
• Section 2: p-InP cladding is reintroduced, and the entire mesa widens from $t_\mathrm{Si} = 220\,\mathrm{nm}$2 to $t_\mathrm{Si} = 220\,\mathrm{nm}$3 over $t_\mathrm{Si} = 220\,\mathrm{nm}$4. The modal field is already well confined, so this taper is short.

A compact realization uses $t_\mathrm{Si} = 220\,\mathrm{nm}$5 and $t_\mathrm{Si} = 220\,\mathrm{nm}$6 ($t_\mathrm{Si} = 220\,\mathrm{nm}$7). An alternative, more fabrication-tolerant design uses $t_\mathrm{Si} = 220\,\mathrm{nm}$8 and $t_\mathrm{Si} = 220\,\mathrm{nm}$9 ($n = 3.455$0).

3. Adiabatic Coupling Theory and Design Formalism

The coupling process is governed by coupled-mode formalism. At each longitudinal position $n = 3.455$1, two supermodes (even/odd) coexist with propagation constants $n = 3.455$2 and $n = 3.455$3. The goal is to maintain all optical power in the evolving local fundamental supermode under adiabatic conditions:

• Adiabatic Condition:

$n = 3.455$4

The instantaneous mode-index split $n = 3.455$5 must remain sufficiently large, and the taper slope $n = 3.455$6 (impacting $n = 3.455$7) must be gentle. Approximate local coupling length is $n = 3.455$8.

• Enforced Design Criterion: $n = 3.455$9 over the entire taper.

This approach suppresses nonadiabatic coupling to undesired supermodes, particularly in Section 1 where high-index contrast and geometry control are critical.

4. Performance Metrics

The VAC’s performance is characterized by several key figures of merit, detailed in the table below:

Metric	Ulracompact Design ($h_\mathrm{BCB} = 0$0)	Tolerant Design ($h_\mathrm{BCB} = 0$1)
Coupling Efficiency $h_\mathrm{BCB} = 0$2	$h_\mathrm{BCB} = 0$3 over $h_\mathrm{BCB} = 0$4–$h_\mathrm{BCB} = 0$5 BW	$h_\mathrm{BCB} = 0$6 over $h_\mathrm{BCB} = 0$7–$h_\mathrm{BCB} = 0$8 BW
Insertion Loss (IL)	$h_\mathrm{BCB} = 0$9	$100\,\mathrm{nm}$0
Reflection Loss (RL)	$100\,\mathrm{nm}$1	$100\,\mathrm{nm}$2
Alignment Tolerance	$100\,\mathrm{nm}$3 (lateral $100\,\mathrm{nm}$4, $100\,\mathrm{nm}$5)	$100\,\mathrm{nm}$6
BCB Thickness Tolerance	$100\,\mathrm{nm}$7 for $100\,\mathrm{nm}$8	$100\,\mathrm{nm}$9 for $n=1.543$0

The bi-sectional taper suppresses higher-order-mode crosstalk to $n=1.543$1–$n=1.543$2 in all modes, while single-section tapers exhibit as low as $n=1.543$3 efficiency and strong undesired mode excitation. For $n=1.543$4, the insertion loss is $n=1.543$5.

5. Fabrication Considerations and Process Tolerances

The VAC is optimized exclusively by patterning the III-V mesa, with the SOI wire kept straight for improved lithographic alignment and overlay simplicity. Key fabrication details include:

• Mask Layout: The taper is implemented within the III-V layer using III-V lithography. SOI waveguide remains $n=1.543$6, unpatterned.
• Overlay Alignment: Alignment marks at the mesa edge facilitate accurate SOI-to-III-V registration.
• Critical Process Parameters:
  • BCB Thickness ($n=1.543$7): Variation ($n=1.543$8–$n=1.543$9) critically affects coupling strength; $150\,\mathrm{nm}$0 is adjusted accordingly.
  • Tip Width Tolerances ($150\,\mathrm{nm}$1/$150\,\mathrm{nm}$2): Variations $150\,\mathrm{nm}$3 impact mode launch overlap; smaller tips reduce high-order excitation but challenge lithography.
  • Etch Depth: SCH and p-InP removal require accuracy within $150\,\mathrm{nm}$4 to avoid optical leakage or nonadiabaticity.

Process inhomogeneity in BCB and tip dimensions constrains the overall yield and spectral response bandwidth.

6. Design Optimization and Trade-offs

Optimization of the VAC is achieved by:

• Semi-3D Taper Principle: Bi-sectional removal of p-cladding maximizes index contrast in the critical first section, allowing ultrashort device lengths.
• Taper Profile: Linear tapers are sufficient for lithographic ease due to large $150\,\mathrm{nm}$5 over most $150\,\mathrm{nm}$6, but nonlinear profiles (quadratic, sine, etc.) could further smooth $150\,\mathrm{nm}$7, reducing scattering.
• Index Engineering: Potential improvement is offered by grading the BCB index using UV-curable polymers to tailor the mode index crossing and further reduce $150\,\mathrm{nm}$8.
• Inverse Design: Application of inverse-design or adjoint optimization methods can minimize VAC footprint within lithographic and process constraints.

Trade-offs arise between minimum footprint (with higher sensitivity to $150\,\mathrm{nm}$9 and operational wavelength) and fabrication tolerance (achieved by increasing $n=3.1667$0). Reflection is further suppressed ($n=3.1667$1) for longer tapers.

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By dividing the III-V taper into two linear segments and omitting the thick p-InP cladding in the initial portion, the VAC achieves ultracompact length ($n=3.1667$2), high efficiency ($n=3.1667$3), broad bandwidth ($n=3.1667$4), low reflection, and robust tolerance to misalignment and BCB thickness, scaling efficiently to Si/III-V photonic integration platforms (Huang et al., 2014).