Unified Analytical Memory Modeling

• Unified analytical memory modeling is a comprehensive framework that employs closed-form and recursive equations to estimate and optimize latency, energy, bandwidth, and capacity trade-offs.
• It integrates scheduling strategies, operand mapping, and device-level nonlinear modeling to support both high-level architectural exploration and low-level circuit integration.
• Validated against silicon and emulators with error margins of 3–10%, the approach scales effectively across heterogeneous accelerators and emerging memory devices.

Unified analytical memory modeling provides a mathematically rigorous and technology-agnostic basis to estimate, optimize, and co-design memory hierarchies across a wide range of hardware, device physics, and workload scales. By abstracting memory systems—from classical DRAM-based hierarchies in DNN accelerators to heterogeneous NPU fabrics and nonlinear device physics—these models enable quantitative evaluation of latency, energy, bandwidth, and capacity trade-offs under concrete scheduling and hardware constraints. This modeling paradigm supports both high-level architecture exploration (cross-layer scheduling, technology selection) and low-level device/circuit integration (e.g., memristor compact models) by unifying the treatment of compute/memory interaction, hierarchical data movement, and physical characteristics into closed-form and/or recursive analytical expressions.

1. Memory Modeling in DNN Accelerators: The DeFiNES Framework

Unified analytical memory modeling emerged as a response to the limitations of piecemeal and myopic cost models that failed to capture the full design space of DNN scheduling and memory hierarchies. DeFiNES formalizes the memory modeling problem along both scheduling and memory axes (Mei et al., 2022):

• Scheduling space: DeFiNES defines single-layer (SL), layer-by-layer (LBL), and depth-first (DF, or layer fusion) execution models. These modes, parameterized by tile size $T=(T_x,T_y)$, overlap-storing mode $m$, and fuse depth $D$, induce diverse data movement and memory capacity patterns.
• Operand/memory hierarchy abstraction: Each unique operand-layer-tile triple $(o,l,t)$ is assigned to exactly one active memory level $m$ (register/PE, local buffer, global buffer, DRAM). Binary variables $x_{o,l,t,m}$ select the assignment subject to per-level capacity constraints:

$$\sum_{o,l,t} x_{o,l,t,m}\,S_{o,l,t} \le C_m \quad\forall m$$

• Analytical cost equations: The number of compute-phase accesses, on-chip/off-chip copy actions, and total memory transactions per level are computed via closed-form expressions, e.g.:

$$N^{\rm comp}_m = \sum_{o,l,t} x_{o,l,t,m} R_{o,l,t} S_{o,l,t}$$

and total energy/latency as

$$E_{\rm total} = \sum_m N_m E_m + E_{\rm MAC} \sum_{l,t} \#\text{MACs}_{l,t}$$

• Optimization and constraints: The optimal schedule is found by minimizing $E_{\rm total}$ or $m$0 over $m$1, subject to capacity, uniqueness, and dataflow ordering constraints.
• Validation: DeFiNES’s predictions (latency within 3–10%, energy within 6%) are validated versus real silicon (DepFiN), demonstrating accurate capture of both on-chip and off-chip trade-offs under both SL/LBL and DF schemes.

DeFiNES’s key contribution is the ability to jointly reason about all levels of the memory hierarchy, operand reuse, and scheduling flexibility under a unifying set of constraints and analytical formulas, significantly improving design space exploration efficiency.

2. Technology-Agnostic Hierarchical Modeling: The MemExplorer Approach

Modern inference NPUs rely on highly heterogeneous memory subsystems (on-chip SRAM, HBM, LPDDR, GDDR, high-bandwidth flash) and increasingly multi-level, multi-device architectures. MemExplorer introduces a unified abstraction that indexes memory types $m$2 with universal parameters: per-stack capacity $m$3, bus width $m$4, I/O frequency $m$5, peak/effective bandwidth $m$6, latency $m$7, leakage power $m$8, and dynamic energy per bit $m$9/$D$0 (Wu et al., 17 Apr 2026).

• Single-level modeling: Each memory type yields closed-form expressions for transfer bandwidth, latency, and power. For instance, latency for a data block $D$1 at level $D$2 is:

$D$3

• Hierarchical recursion and hit-rate composition: Multi-level systems are modeled using recursive transfer recursion (incorporating both overlapping and bandwidth-limited stalls) and, for average access, hit-rate-based formulas.
• Workload-phase folding: Distinct application phases (LLM prefill, decode) are profiled for data transfer and compute-to-communication ratio (CCR), allowing the model to adapt its predictions and technology assignments based on regime.
• Optimization formulation: The design space (memory type assignments, #stacks, bus speeds, engine dimensions) is explored with the objective of maximizing

$D$4

subject to capacity, bandwidth, and power constraints.

• Scalability and solution: The model supports exploration across $D$5–$D$6 possible configurations using Bayesian optimization, heuristics, or mixed-integer optimization.
• Accuracy and generalization: Prediction error is maintained within 10% for end-to-end workloads. The methodology is extended by populating the parameter set for emerging memory technologies or new architectures; the recipe supports straightforward integration and consistent accuracy across diverse stacks.

MemExplorer demonstrates that unified memory modeling is essential for balancing performance, energy efficiency, and device selection in next-generation, heterogeneous accelerator platforms.

3. Analytic Compact Modeling of Device-Level Memory: The HAM-Based Framework

For nonlinear memory devices such as memristors, unified analytical modeling addresses the device scale using the Homotopy Analysis Method (HAM) (Hu et al., 2018):

• Formulation: State dynamics (e.g., HP-memristor’s $D$7) are described by nonlinear ODEs:

$D$8

• HAM construction: The zero-order homotopy introduces a deformation parameter $D$9, an auxiliary convergence parameter $(o,l,t)$0, and produces a series expansion in $(o,l,t)$1, with each term derived via recurrent solution of high-order deformation equations.
• Convergence control: The optimal $(o,l,t)$2 is chosen to minimize the squared residual error over the expansion window, yielding rapid and accurate series convergence even for strongly nonlinear state equations.
• Generality and extensibility: The approach extends to CBRAM, RRAM, PCM, MRAM, and any memory device governed by ODEs $(o,l,t)$3, unifying the treatment of compact models for simulation and circuit integration.
• Quantitative benchmarks: For the HP-memristor with weak nonlinearity ($(o,l,t)$4), HAM-based order-$(o,l,t)$5 models yield $(o,l,t)$6 vs. $(o,l,t)$7 for HPM, with similarly improved RMSE and MRE. For $(o,l,t)$8, HAM convergence remains robust ($(o,l,t)$9), where HPM diverges.
• Circuit embedding: Series solutions are decomposable into DC and harmonic components, supporting compact SPICE subcircuit realization and validation against reference oscillators and waveform generators.

This framework ensures analytic tractability and rapid convergence in nonlinear device modeling, essential for predictive circuit/system-level memory modeling in heterogeneous and emerging devices.

4. Mathematical Structure and Core Equations

Unified analytical memory models across system, architecture, and device scales share several fundamental constructs:

• Data mapping variables: $m$0 for operand-to-memory-level assignment.
• Capacity and bandwidth constraints: Per-level constraints,

$m$1

• Access/transfer recursions: Compute access counts, copies, and transfers between neighboring levels.
• Phase/functions for workload folding: Input/Output data volume, per-phase data transfer, compute-to-communication ratios.
• Objective functions: Latency, energy, and energy efficiency expressions that unify hardware configuration, memory movement, and utilization.
• Optimization and search: Formulate as integer/discrete programming or explore via Bayesian/heuristic methods. Resulting configurations are validated against cycle-accurate emulation or taped-out silicon.
• Device-level series expansions: HAM-based analytic solutions in the form

$m$2

with convergence parameter $m$3 optimized by minimizing

$m$4

This unification of variables, constraints, and cost expressions is the defining characteristic of analytical memory modeling frameworks.

5. Validation, Accuracy, and Extension Across Modalities

Unified analytical memory models are consistently validated against measured silicon, high-fidelity emulators, and for device-scale, circuit simulation platforms:

Framework	Target System	Accuracy Metric	Reported Result
DeFiNES	DepFiN ASIC (DNN)	End-to-end latency/energy	3–10%/6% error
MemExplorer	Emulator vs. NPU	Per-layer latency	≤10% error
HAM (memristor)	MATLAB, HSPICE	MaxRE/MRE/RMSE (order 6)	2.5%/0.8%/0.007

For emerging use cases, the standard workflow is (1) characterize or parameterize the memory technology, (2) populate the abstraction layer, (3) profile the relevant workload, (4) instantiate the hierarchical or ODE-based model, (5) analytically solve or numerically minimize/optimize, and (6) validate and iterate as required (Mei et al., 2022, Wu et al., 17 Apr 2026, Hu et al., 2018).

A plausible implication is that models designed for accelerator-level memory hierarchy exploration and device-level nonlinear ODEs can be systematized within an encompassing analytical methodology, supporting both forward (predictive) and inverse (optimization) design.

6. Impact and Generalization

Unified analytical memory modeling has become foundational in accelerator architecture design, heterogeneous system integration, and compact device modeling. Its extensibility supports rapid incorporation of new memory technologies (e.g., high-bandwidth flash), complex scheduling/idiosyncratic workloads (agentic LLMs, KV-bound inference), and nonlinear device characteristics. The approach delivers:

• Hardware-agnostic, closed-form cost models applicable across compute, architecture, and device layers.
• Proven scalability, tractability, and accuracy, with error rates generally ≤10% under real hardware and emulation.
• Documented generalization procedures for extending models to new memory stacks and device modalities.

These characteristics position unified analytical memory modeling as the de facto backbone for systematic design space exploration, performance/energy optimization, and technology evaluation in high-performance, heterogeneous, and emerging memory-centric computing systems (Mei et al., 2022, Wu et al., 17 Apr 2026, Hu et al., 2018).