TLGLock: Threshold Logic Locking

• TLGLock is a logic-locking methodology that embeds secret keys directly into threshold logic gates using weighted computations to secure circuit functions.
• It integrates threshold logic synthesis with key-dependent arithmetic, yielding a compact design with tunable security-performance trade-offs.
• Implementations using charge-recycling threshold logic demonstrate significant savings in area, delay, and power compared to conventional XOR and latch-based schemes.

TLGLock is a logic-locking methodology that embeds secret keys directly into Threshold Logic Gates (TLGs) rather than attaching external XOR/XNOR key gates, latch blocks, or point-function obfuscation structures. The scheme is presented as a gate-level, stateless, and compact design paradigm that combines threshold-logic synthesis with key-dependent functionality and, in one implementation style, charge recycling. Its stated workflow is to synthesize a Boolean circuit into a TLG-based implementation, select a subset of TLGs to lock, and encode the key into the weighted threshold computation of those gates so that the correct key preserves the intended function while incorrect keys perturb the threshold inequality and corrupt outputs (Sahruri et al., 25 Aug 2025).

1. Conceptual basis

TLGLock is defined by the decision to make locking native to the gate structure. Instead of inserting a separate locking primitive around an already synthesized Boolean network, the method first converts the circuit into threshold logic and then embeds key bits into the gate’s weighted decision rule. The paper describes this as leveraging the structural expressiveness of TLGs and the energy efficiency of charge recycling to enforce key-dependent functionality at the gate level (Sahruri et al., 25 Aug 2025).

This positioning distinguishes TLGLock from several major families of prior logic-locking schemes. In conventional XOR/XNOR locking, keys are attached as explicit logic elements in the combinational network. In latch-based logic locking, by contrast, an interconnected subset of existing flip-flops is converted into pairs of programmable latches, and decoy latches and logic are added so that an attacker cannot easily determine which latch paths implement the real function (Sweeney et al., 2020). TLGLock instead treats the weighted threshold test itself as the locus of obfuscation. The key is not a wrapper around the function; it is part of the function’s arithmetic decision boundary.

The paper situates this design choice as a way to obtain a compact alternative to conventional locking techniques while retaining tunability. A plausible implication is that the threshold-logic representation gives the designer a direct security-performance knob through weight selection and gate selection, rather than only through the number and placement of external key gates.

2. Threshold-logic formulation and key embedding

The computational model begins with the standard threshold-gate form

$$\sum_{j=1}^{m} X_j \times W_j > T \quad \Rightarrow \quad Z=1$$

$$\sum_{j=1}^{m} X_j \times W_j \leq T \quad \Rightarrow \quad Z=0$$

where $X_j \in \{0,1\}$ are inputs, $W_j$ are integer weights, $T$ is the threshold, and $Z$ is the output. The paper also states an equivalent form,

$$\text{Output} = \begin{cases} 1, & \text{if } \sum_{i=1}^{n} w_i \cdot x_i \geq T \ 0, & \text{otherwise} \end{cases}$$

which serves as the basis for the locking transformation (Sahruri et al., 25 Aug 2025).

TLGLock extends this rule by adding key bits as extra weighted inputs:

$$\text{Output} = \begin{cases} 1, & \text{if } \sum_{i=1}^{n} w_i \cdot x_i + \sum_{j=1}^{m} v_j \cdot k_j \geq T \ 0, & \text{otherwise} \end{cases}$$

Here, $x_i$ are functional inputs, $w_i$ their weights, $$\sum_{j=1}^{m} X_j \times W_j \leq T \quad \Rightarrow \quad Z=0$$0 key bits, $$\sum_{j=1}^{m} X_j \times W_j \leq T \quad \Rightarrow \quad Z=0$$1 key weights, and $$\sum_{j=1}^{m} X_j \times W_j \leq T \quad \Rightarrow \quad Z=0$$2 the threshold. With the correct key vector $$\sum_{j=1}^{m} X_j \times W_j \leq T \quad \Rightarrow \quad Z=0$$3, the key contribution is chosen so that the intended threshold behavior is preserved. For an incorrect key vector $$\sum_{j=1}^{m} X_j \times W_j \leq T \quad \Rightarrow \quad Z=0$$4, the weighted sum changes by

$$\sum_{j=1}^{m} X_j \times W_j \leq T \quad \Rightarrow \quad Z=0$$5

and this deviation can move the sum across the threshold, thereby corrupting the output (Sahruri et al., 25 Aug 2025).

The paper illustrates the mechanism with a simple threshold gate:

$$\sum_{j=1}^{m} X_j \times W_j \leq T \quad \Rightarrow \quad Z=0$$6

After key insertion, the same gate becomes

$$\sum_{j=1}^{m} X_j \times W_j \leq T \quad \Rightarrow \quad Z=0$$7

and the correct key $$\sum_{j=1}^{m} X_j \times W_j \leq T \quad \Rightarrow \quad Z=0$$8 is stated to neutralize the effect of the key terms, preserving function (Sahruri et al., 25 Aug 2025).

A notable design point is the key-weight assignment strategy. The authors state that key inputs are embedded with weights proportional to the sum of the input weights. This is intended to make the key terms strong enough to influence whether the threshold is met while still preserving correct functionality under the right key. The paper further reports randomized key-weight experiments showing that corruption is highest for intermediate total key weights, whereas power and delay increase as key weights become more skewed or larger. This suggests that the threshold representation is used not only for embedding but also for tuning the security-overhead trade-off.

3. Synthesis-to-locking flow

The paper presents a complete synthesis-to-locking flow. The stated steps are:

1. Start from a BLIF or BENCH circuit description.
2. Analyze Boolean structure and compute threshold cuts.
3. Synthesize the circuit into TLGs with weights and thresholds.
4. Optionally merge TLGs using linear-combination methods.
5. Embed key inputs into selected gates.
6. Extract and assign weights and thresholds.
7. Map them to the physical TLG implementation.
8. Synthesize, place, and route the locked TLG circuit.
9. Iterate until performance targets are met (Sahruri et al., 25 Aug 2025).

This flow is formalized by two algorithms. In the first stage, the original circuit $$\sum_{j=1}^{m} X_j \times W_j \leq T \quad \Rightarrow \quad Z=0$$9 is synthesized into a TLG circuit $X_j \in \{0,1\}$0, a subset of gates is selected for locking, and a random key vector is generated. The subset size is given as

$X_j \in \{0,1\}$1

where $X_j \in \{0,1\}$2 is the percentage of gates to lock (Sahruri et al., 25 Aug 2025).

In the second stage, each selected gate $X_j \in \{0,1\}$3 is modified by integrating key bits $X_j \in \{0,1\}$4 and corresponding weights $X_j \in \{0,1\}$5. The gate sum is updated as

$X_j \in \{0,1\}$6

and the gate output is then assigned by

$X_j \in \{0,1\}$7

so the lock is directly embedded into the gate’s decision rule (Sahruri et al., 25 Aug 2025).

The stated implementation flow therefore couples logic synthesis and locking more tightly than flows that insert locks into an already fixed netlist. A plausible implication is that TLGLock’s efficacy depends materially on the quality of the threshold synthesis and on how selectively the designer chooses gates and weights.

4. Physical realization in LCTL and CRTL

The paper discusses two physical realizations of threshold logic: LCTL, described as latch-type low-power threshold logic, and CRTL, described as charge-recycling threshold logic. The CRTL realization is central to the title and framing of the method. It uses dynamic charge sharing or recycling to improve power and speed. Conceptually, inputs contribute weighted charge to a threshold decision element, and internal charge is reused during switching rather than fully dissipated each cycle (Sahruri et al., 25 Aug 2025).

In this framework, charge recycling is not itself the locking mechanism. The locking mechanism remains the insertion of key-dependent weighted terms into the threshold inequality. Charge recycling is instead the physical gate technology that carries the locked threshold function efficiently. The paper explicitly states that CRTL is better than LCTL in power and delay while still supporting key embedding (Sahruri et al., 25 Aug 2025).

The reported quantitative comparisons are benchmark-dependent. The abstract states that TLGLock achieves up to 30% area, 50% delay, and 20% power savings compared to latch-based locking schemes (Sahruri et al., 25 Aug 2025). The detailed summary also reports that the conclusion gives up to 29% lower power, 58% faster delay, and 26% area reduction on large designs such as b17 (Sahruri et al., 25 Aug 2025). Example table values in the paper include:

• c17: LCTL at 5 $X_j \in \{0,1\}$8, 2.5 $X_j \in \{0,1\}$9, 1.0 ns; CRTL at 3 $W_j$0, 1.2 $W_j$1, 0.5 ns.
• s386: LCTL at 75 $W_j$2, 35 $W_j$3, 12 ns; CRTL at 50 $W_j$4, 25 $W_j$5, 8 ns.
• b17: LCTL at 7200 $W_j$6, 5000 $W_j$7, 550 ns; CRTL at 6100 $W_j$8, 4000 $W_j$9, 250 ns (Sahruri et al., 25 Aug 2025).

These values are presented as evidence that the charge-recycling implementation gives TLGLock its main efficiency advantage over the latch-controlled threshold-logic variant.

5. Security model, corruption behavior, and SAT evaluation

The security intuition of TLGLock is arithmetic. The output of a TLG is determined by whether a weighted sum crosses a threshold; the key is injected as additional weighted terms; and an incorrect key shifts the weighted sum. When the shifted sum crosses the threshold incorrectly, the output becomes corrupted. The paper defines corruption rate as the percentage of incorrect primary outputs produced when incorrect keys are applied, and states that it is evaluated by exhaustively simulating incorrect key combinations and measuring output mismatch (Sahruri et al., 25 Aug 2025).

Under this metric, the paper reports that TLGLock can reach up to 100% output corruption under incorrect keys. The same section notes that randomized key-weight experiments show the highest corruption for intermediate total key weights, while larger or more skewed weights increase power and delay (Sahruri et al., 25 Aug 2025). This suggests that key weighting acts as a tunable mechanism rather than a fixed recipe.

For attack evaluation, the paper reports SAT analysis with Minisat+ under a 1-hour timeout on ISCAS’85, ISCAS’89, ITC’99, and MCNC benchmarks, implemented in Cadence 45nm GPDK045 (Sahruri et al., 25 Aug 2025). The reported findings include:

• larger circuits such as c1355, c1908, c7552, i10, b17 timed out;
• smaller circuits such as c17, s386, s526, s713 were solvable;
• c2670 and s5378 were reported as UNSAT in the solver run (Sahruri et al., 25 Aug 2025).

The paper states that TLGLock provides up to 3x higher SAT attack resistance than XOR and SFLL-HD baselines, depending on key weights and benchmark (Sahruri et al., 25 Aug 2025). It also explicitly notes an important limitation: SAT resistance is measured by solver runtime and timeout behavior rather than by a formal proof of unbreakability. That caveat is central to interpreting the evaluation. The results indicate empirical hardness for the tested attack configuration, not an unconditional guarantee against deobfuscation.

6. Position within logic-locking research

TLGLock is positioned in the broader logic-locking landscape as a threshold-logic-native alternative to conventional gate-level locking and to sequential locking schemes. The paper says that it borrows from classical logic locking, SAT-resistant locking, threshold logic synthesis, and low-power charge recycling circuits, but makes its main contribution by re-encoding the circuit into threshold gates and embedding the key into the threshold weights (Sahruri et al., 25 Aug 2025).

The comparison against conventional XOR locking and SFLL-HD is summarized by normalized numbers reported in the paper:

Scheme	Normalized SAT time	Normalized area / power / delay
XOR locking	0.1×	baseline
SFLL-HD$T$0	1.0×	2.2× / 1.9× / 1.8×
TLG (W=2–3)	3.0×	1.5× / 1.2× / 1.3×

These figures are presented as the basis for the claim that TLGLock offers a more favorable security-overhead trade-off than the listed baselines (Sahruri et al., 25 Aug 2025).

A relevant sequential comparison point is latch-based logic locking. That method replaces selected flip-flops with pairs of programmable latches, adds path-delay and logic decoy latches, and aims to resist oracle-driven sequential attacks by forcing the attacker to solve phase assignment, timing, reset, and state-space constraints. At 256 bits of locking, it reports average overheads of 1.8% delay, 2.5% power, and 24.1% area without DFT, and 5.0%, 8.3%, and 61.7% with DFT (Sweeney et al., 2020). TLGLock’s abstract comparison to latch-based locking schemes should be read against this background: the two approaches attack different abstraction levels, with latch-based locking manipulating sequential timing and TLGLock modifying threshold-gate decision boundaries (Sahruri et al., 25 Aug 2025).

The paper also implies several limitations. First, the approach depends on the circuit being representable or efficiently transformed into TLG form. Second, the reported results are on standard benchmarks rather than industrial-scale designs. Third, security is empirical rather than formally proved. Fourth, key-weight tuning materially affects both corruption and overhead. Fifth, the claimed implementation benefits depend on the quality of the LCTL or CRTL realization and comparator sizing (Sahruri et al., 25 Aug 2025).

Within those limits, TLGLock is best understood as a logic-locking methodology that moves the secret directly into the weighted threshold computation of the gate. Its distinguishing claim is that threshold logic is not only an implementation substrate but also the mechanism by which the lock is enforced.