TinyNAS: Efficient NAS for TinyML Devices

• TinyNAS is a neural architecture search approach that builds efficient models tailored for microcontrollers with strict memory, latency, and energy limits.
• It utilizes methods like two-stage search, grid search, and zero-shot multi-objective optimization to ensure architectures meet hardware-specific resource budgets.
• TinyNAS frameworks have demonstrated competitive task performance in image classification and time series analysis while reducing search time and energy costs.

TinyNAS refers to a class of neural architecture search (NAS) frameworks specifically designed to yield high-accuracy, resource-efficient deep neural networks suitable for deployment on resource-constrained devices such as microcontrollers (MCUs). These frameworks are characterized by their explicit handling of stringent hardware constraints—memory (SRAM and Flash), latency, and, in many implementations, energy—and their capacity to explore large architecture spaces efficiently, sometimes with zero-shot, evolutionary, or grid-based strategies. TinyNAS was first systematized in the context of MCUNet, but has since been extended, adapted, and generalized in multiple works including TinyTNAS and PrototypeNAS, covering domains beyond image classification, such as time series and general TinyML tasks (Lin et al., 2020, Saha et al., 2024, Deutel et al., 16 Mar 2026).

1. Problem Formulation and Scope

TinyNAS frameworks address the fundamental challenge of enabling deep learning on MCUs and similar edge devices, where available memory ($\approx$ tens to hundreds of kB), Flash ($\approx$ 1–2 MB), and compute throughput are orders of magnitude lower than those available on mobile SoCs. Architectures must not only fit tight resource "budgets" but also deliver competitive accuracy. Formally, the search problem is cast as a constrained multi-objective optimization: $$\max_{\alpha \in \mathcal{S}, w}~ \operatorname{Acc}(\alpha, w)$$ subject to

$$M(\alpha) \le M_{\max}, \quad F(\alpha) \le F_{\max}, \quad T(\alpha) \le T_{\max}, \quad E(\alpha) \le E_{\max}$$

where $\alpha$ parameterizes the architecture (e.g., stage depths, kernels, widths), $w$ the learned weights, $M$ the peak SRAM usage, $F$ the Flash occupation, $T$ the inference latency, and $E$ the energy per inference (Lin et al., 2020, Saha et al., 2024, Deutel et al., 16 Mar 2026).

TinyNAS distinguishes itself from conventional mobile NAS by integrating MCU-specific constraints and by employing search/pruning/quantization spaces and algorithms tailored for sub-megabyte models.

2. Core Methodologies and Search Strategies

TinyNAS and its variants adopt diverse strategies for architecture search and resource compliance:

• Two-Stage Search (MCUNet TinyNAS): First, search-space design is optimized by profiling the valid candidate set under (SRAM, Flash) constraints through simulation. Sub-architectures are sampled and only feasible ones (i.e., $\approx$0, $\approx$1) are retained. Statistical properties (mean FLOPs, etc.) are used to select promising resolution/width multipliers. Subsequently, a one-shot super-network is trained with weight-sharing, followed by an evolutionary search to select Pareto-optimal architectures, which are fully retrained post-selection (Lin et al., 2020).
• Hardware-aware Grid Search (TinyTNAS): For time series classification, TinyTNAS implements a direct, resource-constrained grid search over low-dimensional parameterizations, specifically the filter count ($\approx$2) and the number of repeating blocks ($\approx$3) in a DSC (depthwise-separable convolution) + pooling cascade. At each step, quantized models are profiled for RAM, Flash, and MACs via the MLTK toolkit, and only those meeting user-defined maxima are trained. Time-bound search is explicitly enforced: the process terminates upon hitting a specified wall-clock limit ($\approx$4), returning the highest-accuracy feasible model observed (Saha et al., 2024).
• Zero-Shot, Multi-Objective Optimization (PrototypeNAS): PrototypeNAS generalizes TinyNAS into a three-step pipeline—(1) zero-shot, multi-objective Pareto exploration using proxy signals (SNIP, NASWOT, MeCo, ZiCo), (2) hypervolume-based subset selection to distill representative Pareto-optimal designs, and (3) final model training and quantization. The search space includes macro-architecture choice, width, depth, pruning, and quantization settings, all jointly optimized, yielding candidate models in minutes that outperform prior TinyNAS setups at matched resource budgets (Deutel et al., 16 Mar 2026).
• Device-Aware Resource Profiling: All frameworks profile candidates in situ or via simulation for memory footprint, latency, and energy, tightly coupling NAS to real hardware deployment constraints. For MCUNet, this role is fulfilled by TinyEngine, while TinyTNAS relies on quantized TFLite profiling and MLTK (Lin et al., 2020, Saha et al., 2024).

3. Search Space Design and Model Families

TinyNAS search spaces are expressly constructed for hardware efficiency, leveraging architectural motifs that are both compact and amenable to quantization:

• Mobile-Style Backbones: Inverted-bottleneck (MobileNetV2) structures are preferred, with stage-wise tuning of expansion ratios, kernel sizes (3×3, 5×5, 7×7), and block depths. Channel growth is gradual to avoid bottlenecking memory at any one layer (Lin et al., 2020).
• DSC + Pooling Cascades: For temporal data, TinyTNAS restricts the search space to cell-wise 1D depthwise-separable convolution blocks interleaved with max pooling. Each model is defined by $\approx$5, with geometric filter growth across repeated blocks, followed by global pooling and dense layers (Saha et al., 2024).
• Joint Structure–Compression Spaces: PrototypeNAS augments the macro-architecture dimension (MobileNet, ResNet, SqueezeNet, MbedNet) with algorithmic axes for block-level pruning (sparsity ratios), width scaling, quantization bits (8, 16, 32), and allows group-wise kernel/stride specification. Candidates are thus composite vectors covering structure, pruning, and quantization settings; output channels after compression are $\approx$6 (Deutel et al., 16 Mar 2026).

4. Quantitative Performance and Hardware Evaluation

TinyNAS designs have achieved substantial improvements in resource utilization and accuracy for TinyML tasks:

• ImageNet-1K Classification (MCUNet/TinyNAS): 70.7% top-1 accuracy on STM32H743 ($\approx$795 ms/inference; 466 kB SRAM; 1.2 MB Flash). This result surpassed ResNet-18 and MobileNetV2 under equal or stricter constraints (Lin et al., 2020).
• Time Series Classification (TinyTNAS): On UCI HAR, TinyTNAS reduced RAM by 12× (10.8 kB), MACs by 144× (53.1 k), FLASH by 78× (19.3 kB), and ESP32 inference latency by 149× (13 ms) vs. baseline 1D CNNs, with accuracy increased by 0.2% (93.40%). On PAMAP2/WISDM, similar scale reductions were observed, while on MIT-BIH/PTB, TinyTNAS maintained ≤1–5% accuracy loss with 9× RAM, 64× MAC, and 295× latency reductions (Saha et al., 2024).
• Speed/Profiling: Search times range from ≈10 minutes (TinyTNAS CPU-only time-bound search for time series; PrototypeNAS zero-shot search for joint architecture/compression on small GPUs) to ≈300 GPU-hours (MCUNet super-net training). Energy and CO$\approx$8 costs are greatly lowered vs. traditional RL NAS (e.g., from $\approx$911345 lb to $$\max_{\alpha \in \mathcal{S}, w}~ \operatorname{Acc}(\alpha, w)$$085 lb CO$$\max_{\alpha \in \mathcal{S}, w}~ \operatorname{Acc}(\alpha, w)$$1 per model) (Lin et al., 2020, Saha et al., 2024, Deutel et al., 16 Mar 2026).
• Summary Table: Selected Results

System	Task	Accuracy (%)	RAM (kB)	Flash (kB)	Latency (ms)	References
MCUNet	ImageNet	70.7	466	1200	95	(Lin et al., 2020)
TinyTNAS	UCI HAR	93.40	10.8	19.3	13 (ESP32)	(Saha et al., 2024)
PrototypeNAS	CIFAR-10	90–93.7	112–365	356–775	—	(Deutel et al., 16 Mar 2026)

5. Extensions, Comparative Analysis, and Impact

• Comparisons with Other NAS Approaches: PrototypeNAS provides evidence that, at equivalent resource budgets, it achieves 3–5 percentage points higher accuracy than MCUNet/TinyNAS and NATS-Bench reference models. It attributes these gains to richer search spaces (multiple macro-architectures, joint pruning/quantization) and the use of proxy-based multi-objective optimization (Deutel et al., 16 Mar 2026).
• Broader Applicability: Although initially oriented around image classification, TinyNAS variants (TinyTNAS, PrototypeNAS) have extended the methodology to time series, audio, and object detection tasks, demonstrating the generalizability of the constrained NAS paradigm (Saha et al., 2024, Deutel et al., 16 Mar 2026).
• Deployment and Reproducibility: TinyNAS-generated architectures have been deployed on commercial MCUs (e.g., STM32H743, ESP32, Arduino Nano 33 BLE). Toolkits such as MCUNet’s TinyEngine, TinyTNAS (public GitHub), and MLTK enable end-to-end quantization and hardware profiling (Lin et al., 2020, Saha et al., 2024).

A plausible implication is that TinyNAS principles—hardware profiling in the loop, compact design spaces, resource-aware multi-objective NAS—are central to the mainstreaming of always-on, high-accuracy deep learning at the microcontroller scale.

6. Limitations and Implementation Recommendations

• Search Efficiency: While grid search (TinyTNAS) is highly efficient for low-dimensional parameter spaces, it does not scale to larger or more complex search spaces without the risk of combinatorial explosion. One-shot super-net and zero-shot proxy approaches (MCUNet/PrototypeNAS) are more scalable but require more sophisticated implementation.
• Reliability of Proxies: Zero-shot proxy ensembles (PrototypeNAS) accelerate search but may introduce proxy–accuracy mismatch. However, reported results indicate practical efficacy (Deutel et al., 16 Mar 2026).
• Parameter Tuning: The number of training epochs per candidate can be tuned for a trade-off between search speed and estimate reliability; values of 4–10 have been found effective in practice (Saha et al., 2024).
• Profiling Accuracy: Accurate quantization profiling (e.g., via TF-Lite + MLTK) is essential to ensure searched models meet real hardware constraints post-deployment (Saha et al., 2024).
• Generalizability: TinyNAS’s methodological advances are tightly coupled to MCUs’ unique hardware patterns; direct transfer to mobile or server-class devices requires adaptation (Lin et al., 2020, Deutel et al., 16 Mar 2026).

7. Related Work and Evolution

TinyNAS originated in the context of MCUNet (Lin et al., 2020), representing a landmark in demonstrating >70% ImageNet accuracy on off-the-shelf MCUs. Extensions such as TinyTNAS (Saha et al., 2024) have optimized the approach for CPU-only environments and real-time time series classification, while PrototypeNAS (Deutel et al., 16 Mar 2026) further automates and generalizes TinyNAS through zero-shot, multi-objective search and joint structure–compression spaces. These advances underscore an increasing integration of software, hardware, and search methodology for practical TinyML.

The development trajectory suggests continued convergence of rapid, resource-aware neural architecture search and hardware-centric model specialization, enabling deeper penetration of TinyML into embedded edge AI applications.