MicroNAS: Hardware-Aware Neural Architecture Search

• MicroNAS is a hardware-aware neural architecture search framework that designs MCU-compatible networks fulfilling stringent memory, latency, and energy constraints.
• It employs dynamic search spaces and detailed hardware cost modeling, enabling precise cell design and efficient inference for IoT, wearables, and embedded devices.
• Empirical results demonstrate competitive accuracy and significant efficiency gains, with up to 1100× faster search and reliable performance on resource-constrained platforms.

MicroNAS is a family of hardware-aware neural architecture search (NAS) systems explicitly tailored to generate neural networks that obey the memory and latency constraints of microcontroller units (MCUs), particularly for edge applications in IoT, wearables, and embedded sensor analytics. Unlike traditional NAS efforts that overlook strict real-world device limits, all MicroNAS variants drive model design under explicit SRAM, flash, latency, and, in some cases, energy-use constraints, and deliver architectures deployable on commodity MCUs using lightweight inference frameworks such as TensorFlow Lite Micro.

1. Motivation and Foundational Principles

The proliferation of edge intelligence—including human activity recognition, anomaly detection, and biomedical signal processing—demands ML models that fit the severe resource envelopes of MCUs. Typical MCUs provide tens to hundreds of kilobytes of SRAM, sub-MHz clock rates, and limited flash storage, rendering direct deployment of state-of-the-art desktop neural networks (e.g., DeepConvLSTM, InceptionTime) infeasible due to excessive compute and memory footprints. Cloud offloading introduces latency, energy, and privacy expenses that are incompatible with these domains. The MicroNAS paradigm automates neural network construction to strictly satisfy inference time (e.g., <50 ms) and peak memory (e.g., <32 kB) requirements, while obtaining task accuracy and F1-scores close to unconstrained models (King et al., 2023).

A defining feature of all MicroNAS methods is their tight integration of hardware cost modeling—via lookup tables or analytical proxies—into NAS objectives. This ensures that discovered architectures are not only accurate, but can be deployed directly without further pruning or manual post-hoc compression (King et al., 2023, Liberis et al., 2020, Banbury et al., 2020).

2. Search Space Design and Hardware Cost Proxying

MicroNAS frameworks employ domain-specific or general modular search spaces, with architectural decisions explicitly parameterized to support fine-grained control over network structure and resource usage.

• Cellular Search Spaces: For time-series tasks, networks comprise stacks of two specialized cell types: Time-Reduce cells (temporal context extraction and downsampling using 1D convolutions with variable kernel sizes, strides, and dynamic output channels) and Sensor-Fusion cells (inter-channel feature integration using cross-channel convolutions and multi-branch temporal processing). Discrete options—such as kernel size, filter count, and connection topology—are encoded as differentiable selection variables (e.g., Gumbel-Softmax gating) (King et al., 2023).
• Dynamic Convolutions: MicroNAS leverages dynamic convolution masks inspired by FBNet-v2, enabling smooth interpolation among filter counts through learned soft-gating. The cost estimation for each candidate operation op on the target MCU is computed as

$$\text{op}_{\mathrm{hw}} = \alpha_\gamma^\top \cdot \text{HW}_\text{op} \cdot \alpha_\xi$$

where $\text{HW}_\text{op}$ is an empirical latency/memory matrix (King et al., 2023).

• Latency and Memory Modeling: For accurate resource constraint adherence, MicroNAS precomputes lookup tables mapping parameterized operations (e.g., $(f_\text{in}, f_\text{out})$ pairs for convolutions) to measured cycle counts and memory footprints on target hardware (King et al., 2023, Banbury et al., 2020, Qiao et al., 2024). Alternative methods include using operation count (Ops) or MACs as a linear proxy for latency, justified by high $r^2$ correlations ($>0.95$) between total Ops and measured inference time under uniform backbone priors (Banbury et al., 2020).

3. Optimization Objectives and Search Algorithms

Optimization in MicroNAS systems utilizes either differentiable NAS (DNAS), random/memory-constrained search, or hardware-informed zero-shot pruning. Architectural search proceeds by simultaneously minimizing a task loss (e.g., cross-entropy or F1-based objective) and imposing soft or hard penalties for exceeding hardware budgets.

• Constraint Soft-Penalties: Instead of rejecting infeasible architectures, the loss function introduces continuous penalties that activate only when latency or memory constraints are violated:

$$\mathrm{loss}_{\mathrm{lat}}(\alpha) = \gamma_{\mathrm{lat}}\cdot\log\left(\frac{\mathrm{Lat}(\alpha)}{\mathrm{Lat}_t}\right)\cdot[\mathrm{Lat}(\alpha)\ge\mathrm{Lat}_t]$$

$$\mathrm{loss}_{\mathrm{mem}}(\alpha) = \gamma_{\mathrm{mem}}\cdot\log\left(\frac{\mathrm{Mem}(\alpha)}{\mathrm{Mem}_t}\right)\cdot[\mathrm{Mem}(\alpha)\ge\mathrm{Mem}_t]$$

The complete objective for DNAS is

$$L(\alpha, w) = L_{\mathrm{task}}(\alpha, w) + \mathrm{loss}_{\mathrm{lat}}(\alpha) + \mathrm{loss}_{\mathrm{mem}}(\alpha)$$

with architecture variables $\alpha$ and network weights $w$ updated by gradient descent (King et al., 2023, Banbury et al., 2020).

• Search Algorithms: Frameworks include:
  • Two-loop DNAS (alternating architecture and weight updates; annealing Gumbel-Softmax temperature for sharper decision making).
  • Memory-constrained random search (sample, check budget, and train only valid candidates) (Mohasel et al., 10 Apr 2025).
  • Zero-shot NAS (score architectures using trainability/expressivity proxies such as the Neural Tangent Kernel condition number and ReLU linear region counts, with no weight training, and iteratively prune by score) (Qiao et al., 2024).
  • Pareto-aware evolutionary search with scalarized multitask objectives and dynamic structured pruning (Liberis et al., 2020).

4. Empirical Validation and Performance

MicroNAS demonstrates strong adherence to MCU constraints and maintains competitive classification performance across several datasets and platforms.

• Time Series Classification on MCUs: On Nucleo-F446RE (128 kB SRAM) and Nucleo-L552ZE-Q (256 kB SRAM), MicroNAS achieves quantized F1-scores of 94.1% (UCI-HAR) with latency of 123 ms/15 kB memory, and 95.3% (SkodaR) at 150 ms/19 kB. By contrast, unconstrained desktop models require megabytes of memory and are non-deployable (King et al., 2023).
• Fall Detection Application: For ESP32-S2 (320 kB RAM), MicroNAS discovers both 1D CNN and GRU models for binary fall detection with F1 $\text{HW}_\text{op}$0 0.64–0.66, outperforming ensemble (RUSBoost, EasyEnsemble) and AutoML baselines (by $\text{HW}_\text{op}$1 on statistical tests), while always remaining within the device's RAM budget (Mohasel et al., 10 Apr 2025).
• Zero-Shot NAS Efficiency: On CIFAR-10, MicroNAS (zero-shot variant) finds deployable models in ~0.43 GPU-hours—yielding a 1104× speedup over μNAS—with 3.23× faster MCU inference vs. TE-NAS at matched accuracy (93.8%) (Qiao et al., 2024).
• Resource–Accuracy Trade-offs: Varying allowed latency (10–500 ms) or memory (8–32 kB) in the search leads to monotonic, controllable changes in model accuracy (F1 from 85% to 95% over constrained regimes) (King et al., 2023).
• Comparative Analysis: MicroNAS consistently yields models that better respect hardware budgets and deliver higher or comparable accuracy than post-hoc pruning or generic NAS baselines (e.g., DARTS) (King et al., 2023, Mohasel et al., 10 Apr 2025).

Platform/Dataset	SOTA F1/Acc.	MCU MicroNAS F1/Acc.	SRAM/Flash (KB)	Latency (ms)	Method
Nucleo-F446RE/UCI-HAR	∼0.96	0.941	15	123	(King et al., 2023)
ESP32-S2/Fall Detection	—	0.64–0.66	140–198	—	(Mohasel et al., 10 Apr 2025)
STM32F746ZG/CIFAR-10	0.934	0.9388	0.372	—	(Qiao et al., 2024)
STM32F446RE/VWW	0.881	0.781	69 / 230	181	(Banbury et al., 2020)

5. Extensions, Limitations, and Open Problems

MicroNAS frameworks establish several precedent-setting techniques, but also highlight critical gaps:

• Benefits: Dynamic, domain-specific cell design and soft penalty integration enable efficient search over vast architectural spaces (up to $\text{HW}_\text{op}$2 candidates) in hours, not days (King et al., 2023). Fine-grained dynamic convolution and hardware-informed cost modeling ensure direct deployability on MCUs.
• Limitations: Some variants do not search over non-architectural hyperparameters such as sampling rate, window size, or input channel subset (King et al., 2023). Peak-memory estimation often omits framework overhead (e.g., a few kB in TensorFlow Lite Micro). No current integration of energy or battery constraints; zero-shot proxies may omit memory-stack effects (Qiao et al., 2024). Laboratory evaluation (e.g., simulated fall scenarios) may not fully capture deployment conditions (Mohasel et al., 10 Apr 2025).
• Future Work: Proposed extensions include (i) explicit energy and peak RAM proxy functions, (ii) open-ended or streaming task generalization, (iii) real-world validation on larger, more diverse datasets, (iv) improved data imbalance handling for rare event detection (e.g., adaptive temporal augmentation), and (v) search over non-architectural hyperparameters (King et al., 2023, Mohasel et al., 10 Apr 2025, Qiao et al., 2024).

6. Relation to Prior Art and Broader Impact

The MicroNAS approach emerged following prior generational advancements such as μNAS (Liberis et al., 2020) and MicroNets (Banbury et al., 2020). μNAS pioneered multi-objective evolutionary and Bayesian optimization in an unconstrained connectivity space but required extensive compute (up to 39 GPU-days) and relied on MACs as a linear latency proxy. MicroNets formalized DNAS for TinyML benchmarking, demonstrating a robust linear mapping between operations and observed latency/energy on MCUs, buttressed by empirical resource benchmarking and quantization-aware training.

MicroNAS synthesizes these foundations, introducing memory/latency LUTs, dynamic convolution masking, and domain-specific search spaces, and extends applicability to time-series analysis, fall detection, and general MCU image classification. Its variants have enabled fully automated discovery of MCU deployable classifiers for industrial, biomedical, and IoT domains without cloud dependence, simultaneously advancing SOTA on resource-constrained platforms (King et al., 2023, Mohasel et al., 10 Apr 2025, Qiao et al., 2024).

7. Key Takeaways and Outlook

MicroNAS represents a key advance in hardware-aware neural architecture search for edge deployment, combining differentiable NAS, zero-shot model selection, pervasive quantization, and rigorous hardware cost modeling. Empirical findings demonstrate that memory- and latency-constrained NAS methods, whether DNAS or zero-shot/pruning-based, can discover architectures that approach or even surpass desktop SOTA on tailored tasks, with strict budget adherence and up to 1100× reductions in search cost (Qiao et al., 2024). Ongoing refinement is expected to further bridge the gap between theoretical search objectives and practical deployment, as well as expand the set of real-time, privacy-preserving ML applications possible on MCU-class devices.